| Aging-Aware Instruction-Level Statistical Dynamic Timing Analysis for Embedded Processors. | 0 | 0.34 | 2020 |
| The number of followings as an influential factor in rumor spreading. | 1 | 0.43 | 2019 |
| Instruction-level NBTI Stress Estimation and its Application in Runtime Aging Prediction for Embedded Processors | 0 | 0.34 | 2019 |
| HRSON: Home-based Routing for Smartphones in Opportunistic Networks | 0 | 0.34 | 2019 |
| Evaluating Collaborative Filtering Recommender Algorithms: A Survey. | 0 | 0.34 | 2018 |
| Vulnerability Analysis of Adder Architectures Considering Design and Synthesis Constraints. | 0 | 0.34 | 2018 |
| Evolutionary design for energy-efficient approximate digital circuits. | 0 | 0.34 | 2018 |
| Reliability-Aware Voltage Scaling of Multicore Processors in Dark Silicon Era. | 0 | 0.34 | 2017 |
| A simple multiforce layout for multiplex networks. | 0 | 0.34 | 2016 |
| Fast and accurate architectural vulnerability analysis for embedded processors using Instruction Vulnerability Factor. | 2 | 0.42 | 2016 |
| A Fast Fault-Tolerant Architecture for Sauvola Local Image Thresholding Algorithm Using Stochastic Computing | 13 | 0.68 | 2016 |
| Fast and Accurate FPGA-based Framework for Processor Architecture Vulnerability Analysis | 0 | 0.34 | 2016 |
| Ultralow-Energy Variation-Aware Design: Adder Architecture Study | 2 | 0.39 | 2016 |
| Voltage scaling and dark silicon in symmetric multicore processors | 3 | 0.39 | 2015 |
| An analytical method for reliability aware instruction set extension | 3 | 0.40 | 2014 |
| Customized pipeline and instruction set architecture for embedded processing engines | 1 | 0.35 | 2014 |
| CIVA: Custom instruction vulnerability analysis framework | 2 | 0.36 | 2012 |
| Instruction set architectural guidelines for embedded packet-processing engines | 2 | 0.39 | 2012 |
| Adaptive fault-tolerant DVFS with dynamic online AVF prediction. | 4 | 0.38 | 2012 |
| Design Space Exploration to Find the Optimum Cache and Register File Size for Embedded Applications | 5 | 0.43 | 2012 |
| Vulnerability Analysis for Custom Instructions | 5 | 0.42 | 2012 |
| Performance-optimum superscalar architecture for embedded applications | 0 | 0.34 | 2012 |
| Low-energy GALS NoC with FIFO-Monitoring dynamic voltage scaling | 10 | 0.57 | 2011 |
| Dynamic Voltage and Frequency Scheduling for Embedded Processors Considering Power/Performance Tradeoffs | 18 | 0.78 | 2011 |
| An accurate model for soft error rate estimation considering dynamic voltage and frequency scaling effects | 15 | 0.80 | 2011 |
| Reliability-Aware Dynamic Voltage and Frequency Scaling | 4 | 0.40 | 2010 |
| Architecture-Level Design Space Exploration of Super Scalar Microarchitecture for Network Applications | 0 | 0.34 | 2010 |
| Energy-aware design space exploration of registerfile for extensible processors | 1 | 0.35 | 2010 |
| Instruction reliability analysis for embedded processors | 8 | 0.68 | 2010 |
| Quantitative analysis of packet-processing applications regarding architectural guidelines for network-processing-engine development | 3 | 0.39 | 2009 |
| Design of a Custom Packet Switching Engine for Network Applications | 1 | 0.43 | 2008 |
| Dynamic Voltage and Frequency Management Based on Variable Update Intervals for Frequency Setting | 8 | 0.56 | 2006 |
