| Polite Combination of Algebraic Datatypes | 0 | 0.34 | 2022 |
| Automating System Configuration | 0 | 0.34 | 2021 |
| Politeness And Stable Infiniteness: Stronger Together | 0 | 0.34 | 2021 |
| SAT Solving in the Serverless Cloud | 0 | 0.34 | 2021 |
| Scaling Up Hardware Accelerator Verification using A-QED with Functional Decomposition | 0 | 0.34 | 2021 |
| Counterexample-Guided Prophecy for Model Checking Modulo the Theory of Arrays. | 0 | 0.34 | 2021 |
| Towards Satisfiability Modulo Parametric Bit-vectors | 0 | 0.34 | 2021 |
| Politeness for the Theory of Algebraic Datatypes (Extended Abstract). | 0 | 0.34 | 2021 |
| On Solving Quantified Bit-Vector Constraints Using Invertibility Conditions | 0 | 0.34 | 2021 |
| Algorithms for Verifying Deep Neural Networks | 2 | 0.38 | 2021 |
| An SMT-Based Approach for Verifying Binarized Neural Networks. | 0 | 0.34 | 2021 |
| A Theoretical Framework for Symbolic Quick Error Detection | 0 | 0.34 | 2020 |
| Smt-Switch: a solver-agnostic C++ API for SMT Solving | 0 | 0.34 | 2020 |
| A-QED Verification of Hardware Accelerators | 1 | 0.36 | 2020 |
| Creating An Agile Hardware Design Flow | 0 | 0.34 | 2020 |
| Agile SMT-Based Mapping for CGRAs with Restricted Routing Networks | 0 | 0.34 | 2019 |
| Selected Extended Papers of NFM 2017: Preface. | 0 | 0.34 | 2019 |
| Unlocking the Power of Formal Hardware Verification with CoSA and Symbolic QED - Invited Paper. | 0 | 0.34 | 2019 |
| Symbolic Qed Pre-Silicon Verification For Automotive Microcontroller Cores: Industrial Case Study | 0 | 0.34 | 2019 |
| Syntax-Guided Rewrite Rule Enumeration for SMT Solvers. | 0 | 0.34 | 2019 |
| Invertibility Conditions For Floating-Point Formulas | 1 | 0.36 | 2019 |
| DRAT-based Bit-Vector Proofs in CVC4. | 0 | 0.34 | 2019 |
| Towards Bit-Width-Independent Proofs in SMT Solvers. | 1 | 0.36 | 2019 |
| Refutation-based synthesis in SMT | 4 | 0.47 | 2019 |
| Verifying Deep-RL-Driven Systems. | 3 | 0.40 | 2019 |
| Cvc4sy: Smart And Fast Term Enumeration For Syntax-Guided Synthesis | 3 | 0.39 | 2019 |
| Extending SMT Solvers to Higher-Order Logic. | 1 | 0.35 | 2019 |
| The Marabou Framework For Verification And Analysis Of Deep Neural Networks | 13 | 0.58 | 2019 |
| Algorithms for Verifying Deep Neural Networks. | 4 | 0.38 | 2019 |
| Processor Hardware Security Vulnerabilities And Their Detection By Unique Program Execution Checking | 1 | 0.35 | 2019 |
| High-Level Abstractions For Simplifying Extended String Constraints In Smt | 1 | 0.36 | 2019 |
| G2SAT: Learning to Generate SAT Formulas | 0 | 0.34 | 2019 |
| p4pktgen: Automated Test Case Generation for P4 Programs | 11 | 0.74 | 2018 |
| DeepSafe: A Data-Driven Approach for Assessing Robustness of Neural Networks. | 2 | 0.37 | 2018 |
| EMME: a formal tool for ECMAScript Memory Model Evaluation. | 0 | 0.34 | 2018 |
| CVC4 at the SMT Competition 2018. | 0 | 0.34 | 2018 |
| CoSA: Integrated Verification for Agile Hardware Design | 1 | 0.35 | 2018 |
| Symbolic quick error detection using symbolic initial state for pre-silicon verification | 2 | 0.40 | 2018 |
| Reasoning with Finite Sets and Cardinality Constraints in SMT. | 0 | 0.34 | 2018 |
| Solving Quantified Bit-Vectors Using Invertibility Conditions | 1 | 0.36 | 2018 |
| Toward Scalable Verification for Safety-Critical Deep Networks. | 4 | 0.41 | 2018 |
| Datatypes with Shared Selectors. | 1 | 0.35 | 2018 |
| Constraint Solving for Finite Model Finding in SMT Solvers. | 0 | 0.34 | 2017 |
| Towards Proving The Adversarial Robustness Of Deep Neural Networks | 6 | 0.53 | 2017 |
| Partitioned Memory Models For Program Analysis | 4 | 0.43 | 2017 |
| Logic Bug Detection and Localization Using Symbolic Quick Error Detection. | 0 | 0.34 | 2017 |
| Reluplex: An Efficient Smt Solver For Verifying Deep Neural Networks | 153 | 4.15 | 2017 |
| DeepSafe: A Data-driven Approach for Checking Adversarial Robustness in Neural Networks. | 11 | 0.57 | 2017 |
| Ground-Truth Adversarial Examples. | 0 | 0.34 | 2017 |
| Designing Theory Solvers with Extensions. | 4 | 0.41 | 2017 |
