Parimal A. Patel - Citegraph

Author Info

Name	Affiliation	Papers
PARIMAL A. PATEL	UNIV TEXAS,DIV ENGN,SAN ANTONIO,TX 78249, USA	18
Collaborators	Citations	PageRank
14	21	7.40
Referers	Referees	References
55	58	30

Publications (18 rows)

Collaborators (14 rows)

Referers (55 rows)

Referees (58 rows)

Title	Citations	PageRank	Year
Selection and Implementation of an EAP Authentication Protocol for Hand-held Devices	0	0.34	2008
Optimal XOR hashing for non-uniformly distributed address lookup in computer networks	0	0.34	2007
Distributed IDS using Reconfigurable Hardware	5	0.44	2007
Low Power Implementation of AES (RIJNDAEL) Algorithm	0	0.34	2007
Tutorial IND2A: Embedded Systems Design with Xilinx Virtex-5 Series FPGA	2	0.53	2007
Implementation of an IEEE 802.11i based Wireless Security System	0	0.34	2007
Detecting TCP Port Scans Generated by NMAP using Reconfigurable Hardware	0	0.34	2007
Advanced hashing techniques for non-uniformly distributed IP address lookup	4	0.52	2006
The Design Of Efficient Hashing Techniques For Ip Address Lookup	0	0.34	2006
Embedded systems design using FPGA	3	0.42	2006
Improved Design and Implementation of Network Intrusion Detection System for Gigabit Network Traffic Using FPGA	1	0.39	2005
IDEA cryptographic processor in FPGA	2	0.65	2005
Optimal XOR hashing for a linearly distributed address lookup in computer networks	3	0.45	2005
FPGA Based Implementation of MD5 Message-Digest Algorithm for IPSEC Authentication	0	0.34	2005
17th International Conference on Computer Applications in Industry and Engineering, CAINE 2004, November 17-19, 2004, Florida Mall Hotel, Orlando, Florida, USA	1	0.63	2004
Design And Implementation Of Atm Nic In Fpga	0	0.34	2002
Performance improvement using fill unit	0	0.34	1999
Development of an ASIC Set for Signal Processing	0	0.34	1992

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