Name
Abstract | ||
|---|---|---|
With the rapid growth of computer networks and network infrastructures and increased dependency on the internet to carry out day-to-day activities, it is imperative that the components of the system are secured. In the last few years a number of Intrusion Detection Systems (IDS) have been developed as network security tools, both in commercial and academic sectors. These systems have used different approaches to detecting unauthorized activity, and have given us some insight into the problems that still have to be solved. While considerable progress has been made in the areas of string matching, header processing and detecting DoS attacks at network level, complete systems have not yet been demonstrated that provide all of the functionality necessary to perform intrusion detection at each host system there by securing the entire network. In this paper we are proposing the architecture of a Distributed Intrusion Detection System (DIDS) for use in high-speed networks. The proposed DIDS has Host IDS component at each host that combines the above-mentioned functionalities along with the capability of collecting the events at the application level to look for any signs of intrusion at the network level. DIDS consists of Central IDS component which performs sophisticated processing to detect any signs of distributed attacks on the entire network and update rules in each host system. For high speed networks it can be difficult to keep up with intrusion detection using purely software approach without affecting performance of the system intended for designed application. It is essential to use hardware systems or software with hardware accelerators. The proposed DIDS is a custom hardware implemented on Field Programmable Gate Arrays (FPGAs). This move to customized hardware-based systems allows the introduction of higher degree of parallelism than might be possible in software at a reasonable cost. The key aspects |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1109/IPDPS.2007.370616 | IPDPS |
Keywords | Field | DocType |
dos attack,field programmable gate array,hardware accelerator,parallel processing,reconfigurable hardware,computer networks,intrusion detection,internet,computer network,hardware,fpga,field programmable gate arrays,string matching,software systems,intrusion detection system,network security | Reconfigurability,Denial-of-service attack,Degree of parallelism,Computer science,Computer network,Intrusion detection system,The Internet,Distributed computing,Network security,Parallel computing,Field-programmable gate array,Embedded system,Reconfigurable computing | Conference |
Citations | PageRank | References |
5 | 0.44 | 8 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ashok Kumar Tummala | 1 | 9 | 1.52 |
| Parimal A. Patel | 2 | 21 | 7.40 |