| SafeGuard: Reducing the Security Risk from Row-Hammer via Low-Cost Integrity Protection | 1 | 0.35 | 2022 |
| Tailored Page Sizes | 0 | 0.34 | 2020 |
| Duplicon Cache - Mitigating Off-Chip Memory Bank and Bank Group Conflicts Via Data Duplication. | 0 | 0.34 | 2018 |
| Greater Performance and Better Efficiency: Predicated Execution has shown us the way. | 0 | 0.34 | 2016 |
| Common Bonds: MIPS, HPS, Two-Level Branch Prediction, and Compressed Code RISC Processor. | 0 | 0.34 | 2016 |
| Accelerating Dependent Cache Misses with an Enhanced Memory Controller. | 25 | 0.52 | 2016 |
| Continuous runahead: Transparent hardware acceleration for memory intensive workloads. | 5 | 0.41 | 2016 |
| Filtered runahead execution with a runahead buffer | 4 | 0.37 | 2015 |
| Author retrospective for increasing the instruction fetch rate via multiple branch prediction and a branch address cache | 0 | 0.34 | 2014 |
| Utility-based acceleration of multithreaded applications on asymmetric CMPs | 33 | 0.87 | 2013 |
| MorphCore: An Energy-Efficient Microarchitecture for High Performance ILP and High Throughput TLP | 43 | 1.12 | 2012 |
| Bottleneck identification and scheduling in multithreaded applications | 65 | 1.43 | 2012 |
| Top Picks [Guest editors' introduction] | 9 | 0.71 | 2011 |
| Improving GPU performance via large warps and two-level warp scheduling | 192 | 5.59 | 2011 |
| Prefetch-Aware Memory Controllers | 4 | 0.47 | 2011 |
| Feedback-directed pipeline parallelism | 25 | 0.98 | 2010 |
| The Challenges of Multicore: Information and Mis-Information | 0 | 0.34 | 2009 |
| Coordinated control of multiple prefetchers in multi-core systems | 91 | 2.66 | 2009 |
| Virtual Program Counter (VPC) Prediction: Very Low Cost Indirect Branch Prediction Using Conditional Branch Prediction Hardware | 5 | 0.43 | 2009 |
| Techniques For Bandwidth-Efficient Prefetching Of Linked Data Structures In Hybrid Prefetching Systems | 52 | 1.67 | 2009 |
| Can They Be Fixed: Some Thoughts After 40 Years in the Business | 0 | 0.34 | 2008 |
| Set-Dueling-Controlled Adaptive Insertion for High-Performance Caching | 10 | 0.76 | 2008 |
| VPC prediction: reducing the cost of indirect branches via hardware-based dynamic devirtualization | 26 | 0.86 | 2007 |
| The transformation hierarchy in the era of multi-core | 0 | 0.34 | 2007 |
| Profile-assisted Compiler Support for Dynamic Predication in Diverge-Merge Processors | 7 | 0.50 | 2007 |
| Feedback Directed Prefetching: Improving the Performance and Bandwidth-Efficiency of Hardware Prefetchers | 151 | 5.11 | 2007 |
| Line Distillation: Increasing Cache Capacity by Filtering Unused Words in Cache Lines | 29 | 1.28 | 2007 |
| Address-Value Delta (AVD) Prediction: A Hardware Technique for Efficiently Parallelizing Dependent Cache Misses | 6 | 0.44 | 2006 |
| Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches | 531 | 17.65 | 2006 |
| Diverge-Merge Processor (DMP): Dynamic Predicated Execution of Complex Control-Flow Graphs Based on Frequently Executed Paths | 16 | 0.67 | 2006 |
| Efficient Runahead Execution: Power-Efficient Memory Latency Tolerance | 70 | 2.70 | 2006 |
| A Unifying Theory of Distributed Processing (Or, The Chutzpah One Should Expect When You Invite a Microarchitect into Your Sandbox) | 0 | 0.34 | 2005 |
| Address-Value Delta (AVD) Prediction: Increasing the Effectiveness of Runahead Execution by Exploiting Regular Memory Allocation Patterns | 25 | 0.82 | 2005 |
| The V-Way Cache: Demand Based Associativity via Global Replacement | 89 | 3.95 | 2005 |
| Techniques for Efficient Processing in Runahead Execution Engines | 28 | 1.30 | 2005 |
| Microarchitecture-Based Introspection: A Technique for Transient-Fault Tolerance in Microprocessors | 25 | 1.24 | 2005 |
| Opening and keynote 1 | 0 | 0.34 | 2004 |
| Wrong Path Events: Exploiting Unusual and Illegal Program Behavior for Early Misprediction Detection and Recovery | 11 | 0.75 | 2004 |
| Cache Filtering Techniques to Reduce the Negative Impact of Useless Speculative Memory References on Processor Performance | 8 | 0.55 | 2004 |
| Understanding the effects of wrong-path memory references on processor performance | 13 | 0.64 | 2004 |
| Teaching and teaching computer architecture: two very different topics: (some opinions about each) | 0 | 0.34 | 2003 |
| Handling of packet dependencies: a critical issue for highly parallel network processors | 7 | 0.54 | 2002 |
| Using Internal Redundant Representations and Limited Bypass to Support Pipelined Adders and Register Files | 5 | 0.52 | 2002 |
| Programming early considered harmful | 4 | 0.74 | 2001 |
| Select-free instruction scheduling logic | 76 | 5.91 | 2001 |
| Soft updates: a solution to the metadata update problem in file systems | 54 | 4.17 | 2000 |
| On pipelining dynamic instruction scheduling logic | 67 | 6.03 | 2000 |
| Evaluation of design options for the trace cache fetch mechanism | 18 | 1.37 | 1999 |
| Computer architecture education: mechanical engineers need it too | 0 | 0.34 | 1999 |
| Simultaneous subordinate multithreading (ssmt) | 98 | 6.76 | 1999 |
