Paper Info
Title
SafeGuard: Reducing the Security Risk from Row-Hammer via Low-Cost Integrity Protection
Abstract
Row-Hammer (RH) is a DRAM data-disturbance failure that occurs when a row is activated frequently, which causes bit-flips in nearby rows. Row-Hammer is a significant security threat as an attacker can exploit the bit-flips to do privilege escalation and leak confidential data. While several solutions aim to mitigate RH, such solutions depend on the RH threshold and adversarial access patterns. Solutions developed for a given threshold become ineffective for newer devices with lower thresholds, and new attack patterns continue to break existing mitigations. Currently, there is no guaranteed solution for RH, which means that the system remains vulnerable to security threats even in the presence of RH mitigation.In this paper, we contend that simply relying on RH mitigation is insufficient to provide security in the presence of reducing threshold and motivated attackers. We propose SafeGuard, which equips the system with low-cost integrity protection as a defense against potential attacks that break the RH mitigation. As SafeGuard can detect arbitrary failures, it converts the problem of RH bit-flips from a security threat (silent consumption of corrupted data) to a reliability concern (detectable uncorrectable errors caused by integrity violation). We develop SafeGuard for systems that employ ECC modules and show that SafeGuard can provide strong detection to both SECDED (46-bit MAC per cache-line) and Chipkill (32-bit MAC per cache-line) while retaining the correction capability of conventional designs. SafeGuard avoids incurring any storage overheads in DRAM by simply reorganizing the ECC code to operate at a cache-line granularity (64 bytes) instead of a word granularity (8 bytes). Our evaluations show that SafeGuard has a negligible impact on both the system performance (0.7%) and the system reliability due to naturally occurring errors while still providing a strong defense against the security risk of RH by detecting arbitrary bit-flips.
Year
DOI
Venue
2022
10.1109/HPCA53966.2022.00035
2022 IEEE International Symposium on High-Performance Computer Architecture (HPCA)
Keywords
DocType
ISSN
Row-Hammer,Reliability,Security,Integrity
Conference
1530-0897
ISBN
Citations 
PageRank 
978-1-6654-2028-0
1
0.35
References 
Authors
0
4
Name
Order
Citations
PageRank
Ali Fakhrzadehgan110.35
Yale N. Patt24947566.20
Prashant J. Nair334615.74
Moinuddin K. Qureshi42639110.61