| Spatio-temporal evaluation of epileptic intracranial EEG based on entropy and synchronization: A phase transition idea | 0 | 0.34 | 2022 |
| UH-JLS: A Parallel Ultra-High Throughput JPEG-LS Encoding Architecture for Lossless Image Compression | 0 | 0.34 | 2021 |
| Improving HW/SW Adaptability for Accelerating CNNs on FPGAs Through A Dynamic/Static Co-Reconfiguration Approach | 1 | 0.35 | 2021 |
| WooKong: A Ubiquitous Accelerator for Recommendation Algorithms with Custom Instruction Sets on FPGA | 0 | 0.34 | 2020 |
| A Thread-Oriented Memory Resource Management Framework for Mobile Edge Computing. | 0 | 0.34 | 2019 |
| DCW: A Reactive and Predictable Programming Framework for LET-Based Distributed Real-Time Systems | 0 | 0.34 | 2019 |
| Accelerating Distributed Training in Heterogeneous Clusters via a Straggler-Aware Parameter Server | 0 | 0.34 | 2019 |
| RTMUSRT: a real-time testbed for empirically comparing real-time multicore schedulers: work-in-progress. | 0 | 0.34 | 2018 |
| A Flow-Grained End-to-End Delay Analysis for RC Traffic in TTEthernet. | 0 | 0.34 | 2018 |
| Domino: Graph Processing Services on Energy-Efficient Hardware Accelerator | 1 | 0.36 | 2018 |
| Domino: An Asynchronous and Energy-efficient Accelerator for Graph Processing: (Abstract Only). | 0 | 0.34 | 2018 |
| Impacts of Memory Address Mapping Scheme on Reducing DRAM Self-Refresh Power for Mobile Computing Devices. | 0 | 0.34 | 2018 |
| MuDBN: An Energy-Efficient and High-Performance Multi-FPGA Accelerator for Deep Belief Networks. | 0 | 0.34 | 2018 |
| MALOC: A Fully Pipelined FPGA Accelerator for Convolutional Neural Networks With All Layers Mapped on Chip. | 9 | 0.70 | 2018 |
| UniCNN: A Pipelined Accelerator Towards Uniformed Computing for CNNs. | 0 | 0.34 | 2018 |
| Model checking of MARTE/CCSL time behaviors using timed I/O automata. | 3 | 0.39 | 2018 |
| Hot spots profiling and dataflow analysis in custom dataflow computing SoftProcessors. | 1 | 0.36 | 2017 |
| Exploiting Aperiodic Server to Improve Aperiodic Responsiveness for LET-Based Real-Time Systems | 0 | 0.34 | 2017 |
| A Power-Efficient Accelerator Based on FPGAs for LSTM Network | 2 | 0.37 | 2017 |
| SuperMIC: Analyzing Large Biological Datasets in Bioinformatics with Maximal Information Coefficient. | 1 | 0.35 | 2017 |
| Work-in-Progress: TTI: A Timing ISA for LET Model in Safety-Critical Systems. | 0 | 0.34 | 2017 |
| Clockwerk: A Predictable and Efficient Extension of Logical Execution Time Model | 1 | 0.35 | 2017 |
| Tickwerk: Design of a LET-Based SoC for Temporal Programming. | 0 | 0.34 | 2017 |
| A Power-Efficient Accelerator for Convolutional Neural Networks | 2 | 0.38 | 2017 |
| Implementation and Optimization of the Accelerator Based on FPGA Hardware for LSTM Network | 0 | 0.34 | 2017 |
| A Predictable Servant-Based Execution Model For Safety-Critical Systems | 0 | 0.34 | 2017 |
| Evaluation and Trade-offs of Graph Processing for Cloud Services | 2 | 0.49 | 2017 |
| OmniGraph: A Scalable Hardware Accelerator for Graph Processing | 0 | 0.34 | 2017 |
| FPGA Based Big Data Accelerator Design in Teaching Computer Architecture and Organization. | 0 | 0.34 | 2017 |
| A Time-Aware Programming Framework for Constructing Predictable Real-Time Systems | 0 | 0.34 | 2017 |
| A High-Performance Accelerator for Large-Scale Convolutional Neural Networks | 0 | 0.34 | 2017 |
| Building a Game Benchmark for Cooperative CPU-GPU with Pseudo User-Interaction | 0 | 0.34 | 2017 |
| Genserv: Genome Sequencing Services On Scalable Energy Efficient Accelerators | 1 | 0.44 | 2017 |
| Definitions of predictability for Cyber Physical Systems. | 8 | 0.53 | 2016 |
| Memory Power Optimization on Different Memory Address Mapping Schemas. | 0 | 0.34 | 2016 |
| Soft computing in big data intelligent transportation systems. | 11 | 0.54 | 2016 |
| SCADIS: A Scalable Accelerator for Data-Intensive String Set Matching on FPGAs | 0 | 0.34 | 2016 |
| Heterogeneous Cloud Framework for Big Data Genome Sequencing | 14 | 0.64 | 2015 |
| RapidPath: Accelerating Constrained Shortest Path Finding in Graphs on FPGA (Abstract Only) | 0 | 0.34 | 2015 |
| A case study of parallel JPEG encoding on an FPGA | 0 | 0.34 | 2015 |
| CRAIS: A Crossbar-Based Interconnection Scheme on FPGA for Big Data. | 1 | 0.37 | 2015 |
| Co-processing with dynamic reconfiguration on heterogeneous MPSoC: practices and design tradeoffs (abstract only) | 0 | 0.34 | 2014 |
| Big data genome sequencing on Zynq based clusters (abstract only) | 3 | 0.38 | 2014 |
| Amdahl's and Hill-Marty laws revisited for FPGA-based MPSoCs: from theory to practice | 1 | 0.36 | 2014 |
| Instruction Extension and Generation for Adaptive Processors. | 0 | 0.34 | 2014 |
| Colored Petri Net model with automatic parallelization on real-time multicore architectures | 5 | 0.45 | 2014 |
| PUMA: Pseudo unified memory architecture for single-ISA heterogeneous multi-core systems | 1 | 0.36 | 2014 |
| Temperature-Aware Scheduling Based on Dynamic Time-Slice Scaling. | 0 | 0.34 | 2014 |
| Group Scheduling For Improving Both Cpu And Memory Power Efficiency Simultaneously | 0 | 0.34 | 2013 |
| Detecting Associations in Large Dataset on MapReduce | 1 | 0.35 | 2013 |
