Paper Info
Title
OmniGraph: A Scalable Hardware Accelerator for Graph Processing
Abstract
Large-scale graphs processing attracts more and more attentions, and it has been widely applied in many application domains. FPGA is a promising platform to implement graph processing algorithms with high power-efficiency and parallelism. In this paper, we propose OmniGraph, a scalable hardware accelerator for graph processing. OmniGraph can process graphs with different sizes adaptively and is adaptable to various graph algorithms. OmniGraph improves the preprocessing methodology based on Interval-Shard and consists of three computation engines, vertices on-chip && edges on-chip engine, vertices on-chip && edges off-chip engine, and vertices off-chip && edges off-chip engine. Experimental results on the state-of-the-art Xilinx Virtex-7 board demonstrate that case studies in OmniGraph achieve 1.03x-8.13x average speedup comparing to GraphChi on Intel core2 processors.
Year
DOI
Venue
2017
10.1109/CLUSTER.2017.44
2017 IEEE International Conference on Cluster Computing (CLUSTER)
Keywords
Field
DocType
scalable hardware accelerator,application domains,graph processing algorithms,high power-efficiency,graph algorithms,vertices on-chip,edges on-chip engine,edges off-chip engine,vertices off-chip,OmniGraph,large-scale graphs processing,interval-Shard,Xilinx Virtex-7 board
System on a chip,Vertex (geometry),Computer science,Parallel computing,Field-programmable gate array,Real-time computing,Preprocessor,Hardware acceleration,Systems architecture,Scalability,Speedup
Conference
ISSN
ISBN
Citations 
1552-5244
978-1-5386-2327-5
0
PageRank 
References 
Authors
0.34
6
8
Name
Order
Citations
PageRank
Chongchong Xu174.63
Chao Wang237262.24
Lei Gong36513.52
Yuntao Lu462.59
Fan Sun563.27
Yiwei Zhang65212.65
Xi Li720236.61
Xuehai Zhou855177.54