| Design Space Exploration Based Methodology for Residue Number System Digital Filters Implementation | 0 | 0.34 | 2022 |
| Special Section on Scalable Computing for Blockchain Systems | 0 | 0.34 | 2021 |
| A Reinforcement Learning-Based QAM/PSK Symbol Synchronizer | 0 | 0.34 | 2019 |
| An Efficient Hardware Implementation Of Reinforcement Learning: The Q-Learning Algorithm | 0 | 0.34 | 2019 |
| Tunable Floating-Point Adder | 2 | 0.41 | 2019 |
| Tunable Floating-Point for Energy Efficient Accelerators | 1 | 0.39 | 2018 |
| Tunable Floating-Point for Artificial Neural Networks | 0 | 0.34 | 2018 |
| A Power Efficient Digital Front-End for Cognitive Radio Systems | 0 | 0.34 | 2018 |
| Improved 64-bit Radix-16 Booth Multiplier Based on Partial Product Array Height Reduction. | 3 | 0.57 | 2017 |
| A hardware framework for on-chip FPGA acceleration | 1 | 0.36 | 2016 |
| Dynamically-Loaded Hardware Libraries (Hll) Technology For Audio Applications | 0 | 0.34 | 2016 |
| A framework for dynamically-loaded hardware library (HLL) in FPGA acceleration. | 0 | 0.34 | 2015 |
| Layout-Driven Post-Placement Techniques for Temperature Reduction and Thermal Gradient Minimization | 2 | 0.38 | 2013 |
| Power Efficient Division and Square Root Unit | 10 | 0.69 | 2012 |
| FPGA Based Acceleration of Decimal Operations | 1 | 0.38 | 2011 |
| Post-placement temperature reduction techniques | 1 | 0.36 | 2010 |
| Power Dissipation Challenges In Multicore Floating-Point Units | 2 | 0.51 | 2010 |
| On-chip thermal modeling based on SPICE simulation | 8 | 0.62 | 2009 |
| Division Unit for Binary Integer Decimals | 3 | 0.38 | 2009 |
| ADAPTO: full-adder based reconfigurable architecture for bit level operations | 4 | 0.67 | 2008 |
| A Radix-10 Digit-Recurrence Division Unit: Algorithm and Architecture | 27 | 1.22 | 2007 |
| Low-Power Adaptive Filter Based On Rns Components | 19 | 0.91 | 2007 |
| Programmable power-of-two RNS scaler and its application to a QRNS polyphase filter | 5 | 0.49 | 2005 |
| Low latency digit-recurrence reciprocal and square-root reciprocal algorithm and architecture | 5 | 0.47 | 2005 |
| Digit-Recurrence Dividers with Reduced Logical Depth | 17 | 1.26 | 2005 |
| Low-Power Implementation Of Polyphase Filters In Quadratic Residue Number System | 6 | 0.62 | 2004 |
| Fast radix-4 retimed division with selection by comparisons | 7 | 0.72 | 2002 |
| Cached-code compression for energy minimization in embedded processors | 27 | 1.44 | 2001 |
| Tradeoffs between residue number system and traditional FIR filters | 19 | 2.06 | 2001 |
| FPGA realization of RNS to binary signed conversion architecture | 2 | 0.47 | 2001 |
| Low-Power Division: Comparison among Implementations of Radix 4, 8 and 16 | 3 | 0.48 | 1999 |
| Low-Power Divider | 13 | 1.42 | 1999 |
| Power-delay tradeoffs for radix-4 and radix-8 dividers | 2 | 0.42 | 1998 |
