Name
Abstract | ||
|---|---|---|
Field Programmable Gate-Arrays (FPGAs) can efficiently implement application specific processors in non-conventional number systems, such as the decimal (Binary-Coded Decimal, or BCD) number system required for accounting accuracy in financial applications. The main purpose of this work is to show that applications requiring several decimal (BCD) operations can be accelerated by a processor implemented on a FPGA board connected to the computer by a standard bus. For the case of a telephone billing application, we demonstrate that even a basic implementation of the decimal processor on the FPGA, without an advanced input/output interface, can achieve a speed-up of about 10 over its execution on the CPU of the hosting computer. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/ReConFig.2011.39 | ReConFig |
Keywords | Field | DocType |
decimal operations,telephone billing application,non-conventional number system,number system,field programmable gate-arrays,financial application,binary-coded decimal,application specific processor,accounting accuracy,fpga board,decimal processor,central processing unit,acceleration,hardware,binary coded decimal,field programmable gate array,adders,field programmable gate arrays,input output,benchmark testing | Central processing unit,decimal32 floating-point format,decimal64 floating-point format,Adder,Computer science,Parallel computing,Field-programmable gate array,Acceleration,Computer hardware,Decimal,Benchmark (computing),Embedded system | Conference |
Citations | PageRank | References |
1 | 0.38 | 7 |
Authors | ||
1 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Alberto Nannarelli | 1 | 190 | 20.41 |