Ran Wang - Citegraph

Author Info

Name	Affiliation	Papers
RAN WANG	Duke Univ, Dept ECE, Durham, NC 27708 USA	15
Collaborators	Citations	PageRank
19	42	6.66
Referers	Referees	References
89	323	159

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100323

Publications (15 rows)

Collaborators (19 rows)

Referers (89 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Multicast Testing of Interposer-Based 2.5D ICs: Test-Architecture Design and Test Scheduling.	0	0.34	2018
Tackling Test Challenges for Interposer-Based 2.5-D Integrated Circuits.	1	0.37	2017
ExTest Scheduling and Optimization for 2.5-D SoCs With Wrapped Tiles.	3	0.43	2017
Prebond Testing and Test-Path Design for the Silicon Interposer in 2.5-D ICs.	1	0.34	2017
Testing of Interposer-Based 2.5D Integrated Circuits: Challenges and Solutions	0	0.34	2016
Testing of interposer-based 2.5D integrated circuits.	1	0.63	2016
Multicast Test Architecture and Test Scheduling for Interposer-Based 2.5D ICs	0	0.34	2016
The hype, myths, and realities of testing 3D integrated circuits.	0	0.34	2016
A programmable method for low-power scan shift in SoC integrated circuits	8	0.65	2016
Pre-Bond Testing Of The Silicon Interposer In 2.5d Ics	3	0.43	2016
Interconnect Testing and Test-Path Scheduling for Interposer-Based 2.5-D ICs	1	0.39	2015
Built-In Self-Test and Test Scheduling for Interposer-Based 2.5D IC	11	0.66	2015
At-speed interconnect testing and test-path optimization for 2.5D ICs	7	0.56	2014
Built-in self-test for interposer-based 2.5D ICs	3	0.43	2014
Built-In Self-Test, Diagnosis, and Repair of MultiMode Power Switches	3	0.43	2014

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