Name
Abstract | ||
|---|---|---|
Interposer-based 2.5D integrated circuits (ICs) are seen today as a precursor to 3D ICs based on through-silicon vias (TSVs). All the dies in a 2.5D IC must be adequately tested for product qualification. However, due to the limited number of package pins, it is a a major challenge to test 2.5 ICs using conventional methods. Moreover, due to higher integration levels, test-application time and test power consumption for 2.5D ICs are also increased compared to their 2D counterparts. Therefore, it is imperative to take these issues into account during 2.5D IC testing. In this work, we present an efficient multicast test architecture for targeting defects in dies, in which multiple dies can be tested simultaneously to reduce the test-application time under constraints on test power and fault coverage. We also propose a test scheduling and optimization technique that can be utilized with the multicast test architecture. Compared to previous work, the proposed technique can reduce testapplication time by 53:4% for benchmark designs while achieving higher fault coverage. |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1109/ATS.2016.42 | 2016 IEEE 25th Asian Test Symposium (ATS) |
Keywords | Field | DocType |
multicast test architecture,test scheduling,interposer,integrated circuits,3D IC,through-silicon vias,2.5D IC testing | Architecture,Fault coverage,Computer science,Electronic engineering,Real-time computing,Interposer,Die (manufacturing),Multicast,Test compression,Integrated circuit,Embedded system,Built-in self-test | Conference |
ISSN | ISBN | Citations |
1081-7735 | 978-1-5090-3810-7 | 0 |
PageRank | References | Authors |
0.34 | 0 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Shengcheng Wang | 1 | 13 | 4.29 |
| Ran Wang | 2 | 42 | 6.66 |
| K Chakrabarty | 3 | 8173 | 636.14 |
| Mehdi B. Tahoori | 4 | 1537 | 163.44 |