Author Info
Name
Affiliation
Papers
J.S. YUAN
Chip Design and Reliability Lab, University of Central Florida, Orlando, FL 32816, USA
4
Collaborators
Citations 
PageRank 
8
1
1.38
Referers 
Referees 
References 
2
15
6
Title
Citations
PageRank
Year
PMOS breakdown effects on digital circuits – Modeling and analysis10.372008
Study of performance degradations in DC-DC converter due to hot carrier stress by simulation00.342006
Dynamic voltage stress effects on nMOS varactor00.342006
Hot carrier and soft breakdown effects on LNA performance for ultra wideband communications00.342005