| Three Dimensional Fpga Architecture With Fewer Tsvs | 1 | 0.43 | 2018 |
| Enabling Fpga-As-A-Service In The Cloud With Hcode Platform | 1 | 0.35 | 2018 |
| FPGA based ASIC Emulator with High Speed Optical Serial Links. | 0 | 0.34 | 2017 |
| hCODE 2.0: An open-source toolkit for building efficient FPGA-enabled clouds | 0 | 0.34 | 2017 |
| Physical Fault Detection And Recovery Methods For System-Lsi Loaded Fpga-Ip Core | 0 | 0.34 | 2017 |
| High-level Synthesis based on Parallel Design Patterns using a Functional Language. | 0 | 0.34 | 2017 |
| Towards Open-HW: A Platform to Design, Share and Deploy FPGA Accelerators in Low Cost. | 0 | 0.34 | 2017 |
| A Study of FPGA Virtualization and Accelerator Scheduling | 0 | 0.34 | 2017 |
| hCODE: An open-source platform for FPGA accelerators | 0 | 0.34 | 2016 |
| An area compact soft error resident circuit for FPGA | 0 | 0.34 | 2016 |
| Slm: A Scalable Logic Module Architecture With Less Configuration Memory | 0 | 0.34 | 2016 |
| A novel soft error tolerant FPGA architecture | 0 | 0.34 | 2016 |
| A Study of Heterogeneous Computing Design Method based on Virtualization Technology. | 2 | 0.37 | 2016 |
| Simple wafer stacking 3D-FPGA architecture | 0 | 0.34 | 2015 |
| A 3D FPGA Architecture to Realize Simple Die Stacking. | 0 | 0.34 | 2015 |
| Fault-Tolerant Fpga: Architectures And Design For Programmable Logic Intellectual Property Core In Soc | 1 | 0.36 | 2015 |
| A logic cell architecture exploiting the shannon expansion for the reduction of configuration memory | 2 | 0.42 | 2014 |
| A novel three-dimensional FPGA architecture with high-speed serial communication links | 2 | 0.47 | 2014 |
| An automatic FPGA design and implementation framework | 0 | 0.34 | 2013 |
| Fpga Design Framework Combined With Commercial Vlsi Cad | 4 | 0.58 | 2013 |
| Three-dimensional stacking FPGA architecture using face-to-face integration | 4 | 0.60 | 2013 |
| An Fpga Design And Implementation Framework Combined With Commercial Vlsi Cads | 0 | 0.34 | 2013 |
| A reconfigurable Java accelerator with software compatibility for embedded systems | 0 | 0.34 | 2013 |
| Defect-robust FPGA architectures for intellectual property cores in system LSI. | 0 | 0.34 | 2013 |
| A novel FPGA design framework with VLSI post-routing performance analysis (abstract only) | 0 | 0.34 | 2013 |
| Cogre: A Novel Compact Logic Cell Architecture For Area Minimization | 2 | 0.41 | 2012 |
| A Novel Physical Defects Recovery Technique For Fpga-Ip Cores | 1 | 0.38 | 2012 |
| A bitstream relocation technique to improve flexibility of partial reconfiguration | 9 | 0.60 | 2012 |
| Fault detection and avoidance of FPGA in various granularities. | 1 | 0.36 | 2012 |
| Fault recovery technique for TMR softcore processor system using partial reconfiguration | 0 | 0.34 | 2012 |
| The Evaluation of an Anomaly Detection System Based on Chi-square Method | 2 | 0.38 | 2012 |
| An Easily Testable Routing Architecture And Prototype Chip | 7 | 0.95 | 2012 |
| Designing Flexible Reconfigurable Regions to Relocate Partial Bitstreams | 8 | 0.66 | 2012 |
| Fault-Injection Analysis To Estimate Seu Failure In Time By Using Frame-Based Partial Reconfiguration | 2 | 0.47 | 2012 |
| Improving the Soft-error Tolerability of a Soft-core Processor on. | 0 | 0.34 | 2011 |
| An Easily Testable Routing Architecture and Efficient Test Technique | 4 | 0.61 | 2011 |
| A Novel Soft Error Detection and Correction Circuit for Embedded Reconfigurable Systems | 3 | 0.43 | 2011 |
| An Anomaly Detection System Based on Chi-Square Method with Dynamic BIN Algorithm | 1 | 0.35 | 2011 |
| Parallelization of the channel width search for FPGA routing | 0 | 0.34 | 2011 |
| Comparison of Properties between Entropy and Chi-Square Based Anomaly Detection Method | 0 | 0.34 | 2011 |
| An easily testable routing architecture of FPGA | 1 | 0.37 | 2011 |
| A novel reconfigurable logic device base on 3D stack technology | 3 | 0.53 | 2011 |
| Anomaly Detection Using Chi-square Values Based on the Typical Features and the Time Deviation | 6 | 0.73 | 2011 |
| A Genuine Power-Gatable Reconfigurable Logic Chip With Feram Cells | 2 | 0.53 | 2011 |
| A robust reconfigurable logic device based on less configuration memory logic cell | 5 | 0.61 | 2010 |
| Power-Aware Fpga Routing Fabrics And Design Tools | 1 | 0.36 | 2010 |
| COGRE: A Configuration Memory Reduced Reconfigurable Logic Cell Architecture for Area Minimization | 17 | 1.00 | 2010 |
| Early DoS/DDoS Detection Method using Short-term Statistics | 15 | 0.92 | 2010 |
| Improving the Robustness of a Softcore Processor against SEUs by Using TMR and Partial Reconfiguration | 17 | 1.21 | 2010 |
| A Variable-Grain Logic Cell and Routing Architecture for a Reconfigurable IP Core | 0 | 0.34 | 2010 |
