Name
Abstract | ||
|---|---|---|
In the present study, we investigate the use of reconfigurable logic devices (RLDs) as intellectual properties (IPs) for system on a chip (SoC). Using RLDs, SoCs can achieve both high performance and high flexibility. However, conventional RLDs have problems related to performance, area, and power consumption. In order to resolve these problems, we investigated the features of RLD architecture. RLDs are classified into fine-grained and coarse-grained devices based on their architecture. Generally, the granularity of an RLD is limited to either type, which means that a device can only achieve high performance in applications that are suited to its architecture. Therefore, we propose a variable-grain logic cell (VGLC) architecture that can overcome the trade-off between fine-grained and coarse-grained architectures, which are required for the implementation of random and arithmetic logics, respectively. The VGLC is based on a 4-bit adder including configuration bits, which can perform arithmetic and random logic operations unlike the LUT. In the present paper, a local interconnection architecture for the VGLC is proposed. Several types of local interconnections composed of different crossbars are compared, and the trade-off between hardware resources and flexibility is discussed. Using local interconnection, the routing area is reduced by a maximum of 49%. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1145/1857927.1857932 | TRETS |
Keywords | Field | DocType |
coarse-grained architecture,rld architecture,arithmetic logic,conventional rlds,reconfigurable ip core,coarse-grain,variable-grain logic cell,local interconnection,reconfigurable logic device,fine-grain,reconfigurable ip,high flexibility,high performance,routing architecture,random logic operation,local interconnection architecture,system on a chip,intellectual property,coarse grain | Routing architecture,Lookup table,Architecture,System on a chip,Adder,Computer science,Parallel computing,Real-time computing,Random logic,Granularity,Interconnection,Embedded system | Journal |
Volume | Issue | ISSN |
4 | 1 | 1936-7406 |
Citations | PageRank | References |
0 | 0.34 | 11 |
Authors | ||
7 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kazuki Inoue | 1 | 21 | 5.50 |
| Qian Zhao | 2 | 30 | 10.98 |
| Yasuhiro Okamoto | 3 | 25 | 3.77 |
| Hiroki Yosho | 4 | 4 | 0.95 |
| Motoki Amagasaki | 5 | 121 | 24.78 |
| Masahiro Iida | 6 | 0 | 1.01 |
| Toshinori Sueyoshi | 7 | 226 | 37.13 |