A jumper insertion algorithm under antenna ratio and timing constraints | 1 | 0.35 | 2011 |
Digital Heart-Rate Variability Parameter Monitoring and Assessment ASIC | 0 | 0.34 | 2010 |
Enhancing double-patterning detailed routing with lazy coloring and within-path conflict avoidance | 10 | 0.85 | 2010 |
A case study for NoC-based homogeneous MPSoC architectures | 16 | 0.85 | 2009 |
Adaptive Latency Insensitive Protocols and Elastic Circuits with Early Evaluation: A Comparative Analysis | 5 | 0.48 | 2009 |
Adaptive Latency-Insensitive Protocols | 8 | 0.54 | 2007 |
Floorplanning With Wire Pipelining in Adaptive Communication Channels | 2 | 0.39 | 2006 |
Implementation analysis of NoC: a MPSoC trace-driven approach | 21 | 1.34 | 2006 |
A New System Design Methodology for Wire Pipelined SoC | 1 | 0.35 | 2005 |
Floorplan assisted data rate enhancement through wire pipelining: a real assessment | 1 | 0.35 | 2005 |
Issues in Implementing Latency Insensitive Protocols | 9 | 1.03 | 2004 |
On-chip transparent wire pipelining | 3 | 0.46 | 2004 |
Floorplanning for throughput | 15 | 1.17 | 2004 |
A new approach to latency insensitive design | 45 | 1.70 | 2004 |
A comparison between mask- and field-programmable routing structures on industrial FPGA architectures | 1 | 0.36 | 2004 |
Pipelining Sequential Circuits with Wave Steering | 1 | 0.38 | 2004 |
Layout-driven memory synthesis for embedded systems-on-chip | 43 | 2.58 | 2002 |
Enhanced clustered voltage scaling for low power | 6 | 0.56 | 2002 |
FPGA-Based Fault Injection Techniques for Fast Evaluation of Fault Tolerance in VLSI Circuits | 5 | 0.64 | 2001 |
Low-energy for deep-submicron address buses | 16 | 1.25 | 2001 |
On-the-fly layout generation for PTL macrocells | 18 | 0.94 | 2001 |
A Comment on 'Graph-Based Algorithm for Boolean Function Manipulation' | 1 | 0.63 | 2000 |
A novel high throughput reconfigurable FPGA architecture | 3 | 0.47 | 2000 |
Wave steered FSMs | 5 | 0.59 | 2000 |
Wave-steering one-hot encoded FSMs | 4 | 0.51 | 2000 |