| Setup and Hold Timing Violations Induced by Process Variations, in a Digital Multiplier | 0 | 0.34 | 2008 |
| Metrics for Reconfigurable Architectures Characterization: Remanence and Scalability | 11 | 0.68 | 2003 |
| Post-layout timing simulation of CMOS circuits | 3 | 0.60 | 1993 |
| A Normative Approach to Computer Education: University and Government Cooperate in an Effort to Develop Curriculum | 0 | 0.34 | 1988 |
