Paper Info
Title
Metrics for Reconfigurable Architectures Characterization: Remanence and Scalability
Abstract
Target applications for mobile devices such as PDA and cellular telephones require increasingly powerful architectures. This challenge has spawned different hardware acceleration styles like configurable instruction set processors, coprocessors, and ASIC. Despite acceptable, these solutions show today a lack of flexibility considering rapidly changing standards. Structurally programmable architectures can today provide a trade-off between performance of hardwired logic and flexibility of processors. More and more reconfigurable architectures are today available as IP cores for SoC designers. These ones often differ according to several parameters (granularity, reconfiguration mode, topology...). Therefore, it is not straightforward to compare different architectures and choose the right one considering both actual and future requirements. This paper proposes a general model for reconfigurable architectures and gives a set of metrics which prove useful for architecture characterization. The methodology is illustrated on a dynamically reconfigurable architecture: the systolic ring.
Year
DOI
Venue
2003
10.1109/IPDPS.2003.1213324
IPDPS
Keywords
DocType
ISSN
general model,ip core,reconfigurable architecture,reconfigurable architectures characterization,architecture characterization,different architecture,reconfiguration mode,soc designer,parametrable dynamically reconfigurable architecture,systolic ring,digital signal processing architecture,remanence,performance,scalability,acceleration,mobile device,application specific integrated circuits,metrics,hardware,topology,soc,hardware accelerator,telephony,system on chip,field programmable gate arrays,coprocessors,mobile devices
Conference
1530-2075
ISBN
Citations 
PageRank 
0-7695-1926-1
11
0.68
References 
Authors
4
6
Name
Order
Citations
PageRank
P. Benoit17412.39
G. Sassatelli2838.01
L. Torres3252.46
Didier Demigny4806.30
M. Robert5141.95
G. Cambon6171.53