R. Zhao - Citegraph

Author Info

Name	Affiliation	Papers
R. ZHAO	Zhejiang Univ, Coll Elect Engn, Hangzhou 310027, Zhejiang, Peoples R China	22
Collaborators	Citations	PageRank
62	66	9.41
Referers	Referees	References
172	347	125

Search Limit

100347

Publications (22 rows)

Collaborators (62 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Artificial Working Memory Constructed by Planar 2D Channel Memristors Enabling Brain-Inspired Hierarchical Memory Systems	0	0.34	2022
A raster-based typification method for multiscale visualization of building features considering distribution patterns	0	0.34	2022
Towards Both Accurate and Robust Neural Networks Without Extra Data	0	0.34	2022
Spike-Based Spatiotemporal Processing Enabled by Oscillation Neuron for Energy-Efficient Artificial Sensory Systems	0	0.34	2022
Neuromorphic computing chip with spatiotemporal elasticity for multi-intelligent-tasking robots	0	0.34	2022
Multiresolution Mapping of Land Cover From Remote Sensing Images by Geometric Generalization	0	0.34	2022
Adversarial symmetric GANs: Bridging adversarial samples and adversarial networks	0	0.34	2021
Efficient Design of Spiking Neural Network With STDP Learning Based on Fast CORDIC	1	0.35	2021
ROA: A Rapid Learning Scheme for In-Situ Memristor Networks	0	0.34	2021
Artificial Perception Built On Memristive System: Visual, Auditory, And Tactile Sensations	0	0.34	2020
Racetrack Memory based hybrid Look-Up Table (LUT) for low power reconfigurable computing.	1	0.35	2018
A Two-Step Sensing Circuit for the Hysteresis Loop Selector-Based Resistive Non-Volatile Memory Arrays.	0	0.34	2018
On the design of spectrum shaping codes for high-density data storage	0	0.34	2018
Magnetic Domain-Wall Racetrack Memory-Based Nonvolatile Logic for Low-Power Computing and Fast Run-Time-Reconfiguration.	6	0.54	2016
High-Density and High-Reliability Nonvolatile Field-Programmable Gate Array With Stacked 1D2R RRAM Array	5	0.47	2016
Racetrack Memory-Based Nonvolatile Storage Elements for Multicontext FPGAs.	5	0.42	2016
A Low Power and High Sensing Margin Non-Volatile Full Adder Using Racetrack Memory	8	0.49	2015
A Low Active Leakage and High Reliability Phase Change Memory (PCM) Based Non-Volatile FPGA Storage Element	29	1.34	2014
A Low Power Localized 2T1R STT-MRAM Array With Pipelined Quad-Phase Saving Scheme for Zero Sleep Power Systems	3	0.41	2014
A Low Power Localized 2t1r Stt-Mram Array With Pipelined Quad-Phase Saving Scheme For Zero Sleep Power Systems	1	0.35	2014
STT-MRAM based low power synchronous non-volatile logic with timing demultiplexing	4	0.53	2014
A Novel PWM Control Method for Hybrid-Clamped Multilevel Inverters	3	0.43	2010