Title
STT-MRAM based low power synchronous non-volatile logic with timing demultiplexing
Abstract
The high power and long global interconnection delay are two of the major limits for further scaling down of the process nodes in the very large scale integrated (VLSI) systems. Therefore, new technologies and computer architectures are under focused development to reduce the power consumption and interconnection delay. Magnetic tunnel junction (MTJ) nanopillar with the advantages of non-volatility, fast switching speed, and high density promises new designs and architectures to significantly alleviate the power and delay issues. This paper presents new logic-in-memory designs of the basic logic gates based on MTJs, including INV, (N)AND, (N)OR and XOR. The MTJ sharing and timing demultiplexing techniques are used in the proposed non-volatile logic gates to greatly reduce the write power. The simulation results show that the write power of the proposed non-volatile logic gates is as low as 285fJ/bit. The basic logic gates can finish the read operation in less than 160ps with 4.35f J read energy. Moreover, the proposed non-volatile logic gates may be reconfigured after fabrication, which makes the designs more flexible and robust.
Year
DOI
Venue
2014
10.1109/NANOARCH.2014.6880495
NANOARCH
Keywords
Field
DocType
very large scale integrated systems,xor logic gate,mram devices,(n)or logic gate,timing circuits,logic-in-memory designs,magnetic tunnel junction nanopillar,spin transfer torque magnetic ram,low-power electronics,demultiplexing,stt-mram,timing demultiplexing,cmos logic circuits,logic design,vlsi,low power synchronous nonvolatile logic gates,(n)and logic gate,magnetic tunnelling,logic gates,inv logic gate,sensors,nonvolatile memory,resistance,mnist,stt mram,low power electronics,neuromorphic computing
Logic synthesis,Digital electronics,Logic gate,Pass transistor logic,Computer science,AND-OR-Invert,Parallel computing,Electronic engineering,Logic family,Three-input universal logic gate,Electrical engineering,Diode logic
Conference
ISSN
Citations 
PageRank 
2327-8218
4
0.53
References 
Authors
14
3
Name
Order
Citations
PageRank
Kejie Huang1399.83
R. Zhao2669.41
Yong Lian3394.43