M. Valero - Citegraph

Author Info

Name	Affiliation	Papers
M. VALERO	Computer Architecture Department, Technical University of Catalonia, HiPEAC European Network of Excellence and Barcelona Supercomputing Center	3
Collaborators	Citations	PageRank
13	18	1.61
Referers	Referees	References
54	104	32

Search Limit

100104

Publications (3 rows)

Collaborators (13 rows)

Referers (54 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Architecture performance prediction using evolutionary artificial neural networks	5	0.54	2008
A conflict-free memory banking architecture for fast VOQ packet buffers	2	0.50	2003
Cost-effective compiler directed memory prefetching and bypassing	11	0.57	2002

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