Name
Abstract | ||
|---|---|---|
In order to support the enormous growth of the Internet, innovative research in every router subsystem is needed. We focus our attention on packet buffer design for routers supporting high-speed line rates. More specifically, we address the design of packet buffers using virtual output queuing (VOQ), which are used in most modern router architectures. The design is based on a previously proposed scheme that uses a combination of SRAM and DRAM modules. We propose a storage scheme that achieves a conflict-free memory bank organization. This leads to a reduction of the granularity of DRAM accesses, resulting in a decrease of storage capacity needed by the SRAM. In the DRAM/SRAM scheme, SRAM memory bandwidth needs to fit the line rate. Since memory bandwidth is limited by its size, searching for memory schemes having a small SRAM size arises as an essential issue for high speed line rates (e.g. OC768, 40 Gbps and OC3072, 160 Gbps). |
Year | DOI | Venue |
|---|---|---|
2003 | 10.1109/GLOCOM.2003.1259010 | Global Telecommunications Conference, 2003. GLOBECOM '03. IEEE |
Keywords | Field | DocType |
DRAM chips,SRAM chips,buffer storage,electronic switching systems,memory architecture,queueing theory,160 Gbit/s,40 Gbit/s,DRAM modules,Internet,OC3072,OC768,SRAM modules,VOQ packet buffers,high speed switches,line rate,memory bandwidth,memory bank architecture,router subsystem,storage capacity | Dram,Memory bank,Memory bandwidth,Computer science,Network packet,Computer network,Real-time computing,Universal memory,Static random-access memory,Router,Memory architecture,Embedded system | Conference |
Volume | ISBN | Citations |
7 | 0-7803-7974-8 | 2 |
PageRank | References | Authors |
0.50 | 5 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jorge García | 1 | 56 | 9.36 |
| Llorenç Cerdà | 2 | 2 | 0.50 |
| Jesús Corbal | 3 | 2 | 0.50 |
| M. Valero | 4 | 18 | 1.61 |