Hiroshi Nakamura - Citegraph

Author Info

Name	Affiliation	Papers
HIROSHI NAKAMURA	Univ Tokyo, Tokyo 1138656, Japan	23
Collaborators	Citations	PageRank
44	49	9.36
Referers	Referees	References
168	573	191

Search Limit

100573

Publications (23 rows)

Collaborators (44 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
An Energy-Efficient Task Scheduling For Near Real-Time Systems On Heterogeneous Multicore Processors	0	0.34	2020
Power Management of Wireless Sensor Nodes with Coordinated Distributed Reinforcement Learning	0	0.34	2019
Adaptive Power Management in Solar Energy Harvesting Sensor Node Using Reinforcement Learning.	10	0.58	2017
Scalable deep neural network accelerator cores with cubic integration using through chip interface	0	0.34	2017
An Energy-Efficient Task Scheduling For Near-Realtime Systems With Execution Time Variation	0	0.34	2017
Building block multi-chip systems using inductive coupling through chip interface	0	0.34	2017
Normally-Off Power Management For Sensor Nodes Of Global Navigation Satellite System	0	0.34	2016
An adaptive energy-efficient task scheduling under execution time variation based on statistical analysis	0	0.34	2016
Profile-based power shifting in interconnection networks with on/off links	0	0.34	2015
Runtime multi-optimizations for energy efficient on-chip interconnections1	0	0.34	2015
Energy-Efficient Continuous Task Scheduling for Near Real-Time Periodic Tasks.	1	0.36	2015
Performance estimation of high performance computing systems with Energy Efficient Ethernet technology	2	0.38	2014
Normally-off computing project: Challenges and opportunities	1	0.35	2014
Area-Efficient Microarchitecture For Reinforcement Of Turbo Mode	0	0.34	2014
Performance modeling for designing NoC-based multiprocessors	1	0.43	2013
McRouter: Multicast within a router for high performance network-on-chips	1	0.36	2013
Improving fairness, throughput and energy-efficiency on a chip multiprocessor through DVFS	15	0.75	2007
An intra-task dvfs technique based on statistical analysis of hardware events	10	0.76	2007
Energy-Efficient Dynamic Instruction Scheduling Logic Through Instruction Grouping	4	0.47	2006
Performance optimization of synchronous control units for datapaths with variable delay arithmetic units	3	0.51	2003
Control Signal Sharing Using Data-Path Delay Information at Control Data Flow Graph Descriptions	0	0.34	2003
Control signal sharing of asynchronous circuits using datapath delay information	0	0.34	2003
Design and evaluation of high performance microprocessor with reconfigurable on-chip memory	1	0.37	2002