Title | ||
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Performance optimization of synchronous control units for datapaths with variable delay arithmetic units |
Abstract | ||
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Nowadays, variable delay arithmetic units have been used for implementing a datapath of a target system in pursuit of performance improvement. However, adoption of variable delay arithmetic units requires modification of a typical synchronous control unit design methodology. A telescopic arithmetic unit based methodology is one of representative methodologies to design synchronous control units for variable delay datapaths. In this paper, we propose two optimization methods for it. Proposed optimization techniques will be analyzed in order to show their performance improvement effects explicitly. |
Year | DOI | Venue |
---|---|---|
2003 | 10.1145/1119772.1119952 | ASP-DAC |
Keywords | Field | DocType |
performance improvement effect,performance improvement,representative methodology,variable delay datapaths,synchronous control unit,performance optimization,design methodology,proposed optimization technique,variable delay arithmetic unit,optimization method,telescopic arithmetic unit,finite state machines,standard cell,logic design | Logic synthesis,Synchronous control,Datapath,Computer science,Arithmetic,Arithmetic logic unit,Electronic engineering,Real-time computing,Finite-state machine,Design methods,Standard cell,Performance improvement | Conference |
ISBN | Citations | PageRank |
0-7803-7660-9 | 3 | 0.51 |
References | Authors | |
5 | 6 |
Name | Order | Citations | PageRank |
---|---|---|---|
Euiseok Kim | 1 | 46 | 10.09 |
Dongik Lee | 2 | 77 | 14.46 |
Hiroshi Saito | 3 | 21 | 6.61 |
Hiroshi Nakamura | 4 | 49 | 9.36 |
Jeong-Gun Lee | 5 | 72 | 18.27 |
Takashi Nanya | 6 | 200 | 35.46 |