Weiwen Jiang - Citegraph

Author Info

Name	Affiliation	Papers
WEIWEN JIANG	College of Computer Science, Chongqing University, Chongqing, China	42
Collaborators	Citations	PageRank
123	95	16.21
Referers	Referees	References
277	758	310

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100758

Publications (42 rows)

Collaborators (100 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
A length adaptive algorithm-hardware co-design of transformer on FPGA through sparse attention and dynamic pipelining	0	0.34	2022
Dancing along Battery: Enabling Transformer with Run-time Reconfigurability on Mobile Devices	0	0.34	2021
Device-Circuit-Architecture Co-Exploration for Computing-in-Memory Neural Accelerators	3	0.38	2021
Accelerating Transformer-based Deep Learning Models on FPGAs using Column Balanced Block Pruning	3	0.40	2021
One Proxy Device Is Enough for Hardware-Aware Neural Architecture Search	1	0.35	2021
Can Noise on Qubits Be Learned in Quantum Neural Network? A Case Study on QuantumFlow (Invited Paper)	0	0.34	2021
FL-DISCO: Federated Generative Adversarial Network for Graph-based Molecule Drug Discovery (Special Session Paper)	0	0.34	2021
Privacy-Preserving Medical Image Segmentation via Hybrid Trusted Execution Environment	0	0.34	2021
Work in Progress: Mobile or FPGA? A Comprehensive Evaluation on Energy Efficiency and a Unified Optimization Framework	0	0.34	2021
A Compression-Compilation Framework for On-mobile Real-time BERT Applications.	0	0.34	2021
DIAN: differentiable accelerator-network co-search towards maximal DNN efficiency	0	0.34	2021
A mining pool solution for novel proof-of-neural-architecture consensus	0	0.34	2021
When Machine Learning Meets Quantum Computers: A Case Study	0	0.34	2021
Optimizing FPGA-based Accelerator Design for Large-Scale Molecular Similarity Search (Special Session Paper)	0	0.34	2021
RMSMP - A Novel Deep Neural Network Quantization Framework with Row-wise Mixed Schemes and Multiple Precisions.	0	0.34	2021
Exploration of Quantum Neural Architecture by Mixing Quantum Neuron Designs	0	0.34	2021
Co-Exploring Neural Architecture and Network-on-Chip Design for Real-Time Artificial Intelligence	3	0.43	2020
Towards Cardiac Intervention Assistance: Hardware-aware Neural Architecture Exploration for Real-Time 3D Cardiac Cine MRI Segmentation	0	0.34	2020
Towards the design of efficient hash-based indexing scheme for growing databases on non-volatile memory	0	0.34	2020
Standing on the Shoulders of Giants: Hardware and Neural Architecture Co-Search With Hot Start	4	0.45	2020
Co-Exploration Of Neural Architectures And Heterogeneous Asic Accelerator Designs Targeting Multiple Tasks	0	0.34	2020
Achieving Full Parallelism in LSTM via a Unified Accelerator Design	0	0.34	2020
Hardware/Software Co-Exploration of Neural Architectures	11	0.59	2020
Accuracy vs. Efficiency: Achieving Both through FPGA-Implementation Aware Neural Architecture Search	17	0.74	2019
Achieving Super-Linear Speedup across Multi-FPGA for Real-Time DNN Inference	10	0.54	2019
XFER - A Novel Design to Achieve Super-Linear Performance on Multiple FPGAs for Real-Time AI.	3	0.44	2019
When Neural Architecture Search Meets Hardware Implementation: from Hardware Awareness to Co-Design	3	0.40	2019
Synthesizing distributed pipelining systems with timing constraints via optimal functional unit assignment and communication selection.	1	0.35	2018
UMFS: An efficient user-space file system for non-volatile memory.	1	0.35	2018
Thermal-Aware Task Mapping on Dynamically Reconfigurable Network-on-Chip Based Multiprocessor System-on-Chip.	4	0.43	2018
Communication optimization for thermal reliable many-core systems: work-in-progress	0	0.34	2017
A New Design of In-Memory File System Based on File Virtual Address Framework.	15	0.61	2016
Properties of Self-Timed Ring Architectures for Deadlock-Free and Consistent Configuration Reaching Maximum Throughput	3	0.40	2016
The design of an efficient swap mechanism for hybrid DRAM-NVM systems.	3	0.38	2016
Optimal functional-unit assignment and buffer placement for probabilistic pipelines.	2	0.38	2016
On the Design of High-Performance and Energy-Efficient Probabilistic Self-Timed Systems	3	0.37	2015
Prevent Deadlock and Remove Blocking for Self-Timed Systems.	0	0.34	2015
Designing an efficient persistent in-memory file system	3	0.40	2015
Contention-aware task and communication co-scheduling for network-on-chip based Multiprocessor System-on-Chip	0	0.34	2014
On self-timed ring for consistent mapping and maximum throughput	0	0.34	2014
An Improved Thermal Model for Static Optimization of Application Mapping and Scheduling in Multiprocessor System-on-Chip	1	0.36	2014
Effective file data-block placement for different types of page cache on hybrid main memory architectures	1	0.36	2013