Name
Title | ||
|---|---|---|
Accuracy vs. Efficiency: Achieving Both through FPGA-Implementation Aware Neural Architecture Search |
Abstract | ||
|---|---|---|
A fundamental question lies in almost every application of deep neural networks: what is the optimal neural architecture given a specific data set? Recently, several Neural Architecture Search (NAS) frameworks have been developed that use reinforcement learning and evolutionary algorithm to search for the solution. However, most of them take a long time to find the optimal architecture due to the huge search space and the lengthy training process needed to evaluate each candidate. In addition, most of them aim at accuracy only and do not take into consideration the hardware that will be used to implement the architecture. This will potentially lead to excessive latencies beyond specifications, rendering the resulting architectures useless. To address both issues, in this paper we use Field Programmable Gate Arrays (FPGAs) as a vehicle to present a novel hardware-aware NAS framework, namely FNAS, which will provide an optimal neural architecture with latency guaranteed to meet the specification. In addition, with a performance abstraction model to analyze the latency of neural architectures without training, our framework can quickly prune architectures that do not satisfy the specification, leading to higher efficiency. Experimental results on common data set such as ImageNet show that in the cases where the state-of-the-art generates architectures with latencies 7.81× longer than the specification, those from FNAS can meet the specs with less than 1% accuracy loss. Moreover, FNAS also achieves up to 11.13× speedup for the search process. To the best of the authors' knowledge, this is the very first hardware aware NAS.
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Year | DOI | Venue |
|---|---|---|
2019 | 10.1145/3316781.3317757 | Proceedings of the 56th Annual Design Automation Conference 2019 |
Keywords | Field | DocType |
deep neural networks,search process,search space,FPGA-implementation aware neural architecture search,hardware-aware NAS framework,field programmable gate arrays,reinforcement learning,evolutionary algorithm | Architecture,Evolutionary algorithm,Latency (engineering),Computer science,Field-programmable gate array,Real-time computing,Electronic design automation,Rendering (computer graphics),Computer engineering,Speedup,Reinforcement learning | Journal |
Volume | ISSN | ISBN |
abs/1901.11211 | 0738-100X | 978-1-4503-6725-7 |
Citations | PageRank | References |
17 | 0.74 | 8 |
Authors | ||
7 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Weiwen Jiang | 1 | 95 | 16.21 |
| Xinyi Zhang | 2 | 20 | 1.85 |
| Edwin H.-M. Sha | 3 | 1318 | 97.35 |
| Lei Yang | 4 | 105 | 11.42 |
| Qingfeng Zhuge | 5 | 42 | 8.11 |
| Yiyu Shi | 6 | 553 | 83.22 |
| Jingtong Hu | 7 | 963 | 76.16 |