FCDM: A Methodology Based on Sensor Pattern Noise Fingerprinting for Fast Confidence Detection to Adversarial Attacks | 0 | 0.34 | 2020 |
BRLoop: Constructing balanced retimed loop to architect STT-RAM-based hybrid cache for VLIW processors. | 1 | 0.35 | 2019 |
Fast Confidence Detection - One Hot Way to Detect Adversarial Attacks via Sensor Pattern Noise Fingerprinting. | 0 | 0.34 | 2019 |
Redesigning pipeline when architecting STT-RAM as registers in rad-hard environment | 0 | 0.34 | 2019 |
A Dual-Threshold Scheme Along with Security Reinforcement for Energy Efficient Nonvolatile Processors | 1 | 0.36 | 2018 |
Taming the "Monster": Overcoming Program Optimization Challenges on SW26010 Through Precise Performance Modeling | 1 | 0.35 | 2018 |
A Pipelining Loop Optimization Method for Dataflow Architecture. | 3 | 0.39 | 2018 |
Rethinking manycore caches for scale-out applications. | 0 | 0.34 | 2015 |
Optimizing mapreduce with low memory requirements for shared-memory systems | 0 | 0.34 | 2014 |