Jian-Bin Zhou - Citegraph

Author Info

Name	Affiliation	Papers
JIAN-BIN ZHOU	Waseda Univ, Grad Sch Informat Prod & Syst, 2-7 Hibikino, Kitakyushu, Fukuoka 8080135, Japan	12
Collaborators	Citations	PageRank
16	23	4.66
Referers	Referees	References
74	204	103

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100204

Publications (12 rows)

Collaborators (16 rows)

Referers (74 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Approximate-Dct-Derived Measurement Matrices With Row-Operation-Based Measurement Compression And Its Vlsi Architecture For Compressed Sensing	0	0.34	2018
VLSI Implementation of HEVC Motion Compensation With Distance Biased Direct Cache Mapping for 8K UHDTV Applications.	4	0.38	2017
An 8K H.265/HEVC Video Decoder Chip With a New System Pipeline Design.	2	0.37	2017
Framework And Vlsi Architecture Of Measurement-Domain Intra Prediction For Compressively Sensed Visual Contents	0	0.34	2017
Measurement-domain intra prediction framework for compressively sensed images	1	0.47	2017
A Dual-Clock VLSI Design of H.265 Sample Adaptive Offset Estimation for 8k Ultra-HD TV Encoding	2	0.38	2017
Approximate-Dct-Derived Measurement Matrices For Compressed Sensing	0	0.34	2017
14.7 A 4Gpixel/s 8/10b H.265/HEVC video decoder chip for 8K Ultra HD applications.	7	0.48	2016
High Performance Vlsi Architecture Of H.265/Hevc Intra Prediction For 8k Uhdtv Video Decoder	4	0.49	2015
Unified Parameter Decoder Architecture For H.265/Hevc Motion Vector And Boundary Strength Decoding	1	0.35	2015
Unified VLSI Architecture of Motion Vector and Boundary Strength Parameter Decoder for 8K UHDTV HEVC Decoder	2	0.39	2014
VLSI architecture of HEVC intra prediction for 8K UHDTV applications	0	0.34	2014

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