| 7.2 4Mb STT-MRAM-based cache with memory-access-aware power optimization and write-verify-write / read-modify-write scheme | 6 | 0.46 | 2016 |
| 7.5 A 3.3ns-access-time 71.2μW/MHz 1Mb embedded STT-MRAM using physically eliminated read-disturb scheme and normally-off memory architecture | 16 | 1.10 | 2015 |
| Highly reliable and low-power nonvolatile cache memory with advanced perpendicular STT-MRAM for high-performance CPU | 20 | 2.85 | 2014 |
