Name
Title | ||
|---|---|---|
Highly reliable and low-power nonvolatile cache memory with advanced perpendicular STT-MRAM for high-performance CPU |
Abstract | ||
|---|---|---|
This paper presents a novel nonvolatile last level cache (LLC) based on the advanced perpendicular STT-MRAM to reduce the total power consumption of LLC. The presented LLC has novel readout circuit with the dual-sensing salvation scheme that enhances reliability of STT-MRAM along with typical error-correcting code (ECC). The comparison of CPU performance per power with SRAM-based, embedded DRAM and conventional STT-MRAM-based LLCs indicates that the presented novel nonvolatile LLC is the most suitable for large LLC. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/VLSIC.2014.6858403 | VLSIC |
Field | DocType | Citations |
Dram,Semiconductor memory,Perpendicular,Computer performance,CPU cache,Computer science,Cache,Parallel computing,Magnetoresistive random-access memory,Computer hardware,Embedded system,Power consumption | Conference | 20 |
PageRank | References | Authors |
2.85 | 0 | 6 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Hiroki Noguchi | 1 | 145 | 20.04 |
| Kazutaka Ikegami | 2 | 43 | 6.79 |
| Naoharu Shimomura | 3 | 47 | 6.49 |
| Tetsufumi Tanamoto | 4 | 24 | 6.40 |
| Junichi Ito | 5 | 42 | 4.41 |
| Shinobu Fujita | 6 | 180 | 22.11 |