Author Info
Name
Affiliation
Papers
DARLENE VIVIANI
Department of Electrical, Electronic, and Communication Engineering, Graduate School of Science and Engineering, Chuo University, Tokyo, Japan
1
Collaborators
Citations 
PageRank 
7
0
0.34
Referers 
Referees 
References 
0
49
13
Title
Citations
PageRank
Year
Reset-Check-Reverse-Flag Scheme on NRAM With 50% Bit Error Rate or 35% Parity Overhead and 16% Decoding Latency Reductions for Read-Intensive Storage Class Memory.00.342016