Name
Title | ||
|---|---|---|
Reset-Check-Reverse-Flag Scheme on NRAM With 50% Bit Error Rate or 35% Parity Overhead and 16% Decoding Latency Reductions for Read-Intensive Storage Class Memory. |
Abstract | ||
|---|---|---|
A novel error correction scheme, called reset-checkreverse-flag (RCRF), is proposed to improve the reliability of storage class memories (SCMs). RCRF divides the conventional Bose-Chaudhuri-Hocquenghem (BCH) code length into multiple subsections. One flag bit is added to each subsection to correct program errors. By reversing the flag bit and user data, at least one reset error in each subsection ... |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1109/JSSC.2016.2561966 | IEEE Journal of Solid-State Circuits |
Keywords | Field | DocType |
Error correction codes,Microprocessors,Bit error rate,Decoding,Error correction,Arrays | Resistive touchscreen,Computer science,Error detection and correction,Chip,BCH code,Decoding methods,Computer hardware,Megabit,Bit error rate,Resistive random-access memory | Journal |
Volume | Issue | ISSN |
51 | 8 | 0018-9200 |
Citations | PageRank | References |
0 | 0.34 | 13 |
Authors | ||
8 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Sheyang Ning | 1 | 11 | 2.95 |
| Tomoko Ogura Iwasaki | 2 | 1 | 0.70 |
| Shuhei Tanakamaru | 3 | 121 | 18.35 |
| Darlene Viviani | 4 | 0 | 0.34 |
| Henry Huang | 5 | 0 | 0.34 |
| monte manning | 6 | 2 | 0.73 |
| thomas rueckes | 7 | 2 | 0.73 |
| Ken Takeuchi | 8 | 88 | 43.27 |