A. Levisse - Citegraph

Author Info

Name	Affiliation	Papers
A. LEVISSE	Univ. Grenoble Alpes, MINATEC Campus, Grenoble, France	22
Collaborators	Citations	PageRank
72	25	8.74
Referers	Referees	References
67	351	55

Search Limit

100351

Publications (22 rows)

Collaborators (72 rows)

Referers (67 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Running Efficiently CNNs on the Edge Thanks to Hybrid SRAM-RRAM In-Memory Computing.	0	0.34	2021
Exact Neural Networks from Inexact Multipliers via Fibonacci Weight Encoding	0	0.34	2021
Architecting more than Moore: wireless plasticity for massive heterogeneous computer architectures (WiPLASH)	0	0.34	2021
A Flexible In-Memory Computing Architecture for Heterogeneously Quantized CNNs	2	0.43	2021
BLADE: An in-Cache Computing Architecture for Edge Devices	6	0.43	2020
Towards Deeply Scaled 3D MPSoCs with Integrated Flow Cell Array Technology	0	0.34	2020
Analysis of Functional Errors Produced by Long-Term Workload-Dependent BTI Degradation in Ultralow Power Processors	0	0.34	2020
RRAM-VAC: A Variability-Aware Controller for RRAM-based Memory Architectures	0	0.34	2020
Enabling Optimal Power Generation of Flow Cell Arrays in 3D MPSoCs with On-Chip Switched Capacitor Converters	0	0.34	2020
A Hybrid Cache HW/SW Stack for Optimizing Neural Network Runtime, Power and Endurance	0	0.34	2020
BLADE: A BitLine Accelerator for Devices on the Edge	1	0.51	2019
A Fast, Reliable and Wide-Voltage-Range In-Memory Computing Architecture	3	0.58	2019
Functionality Enhanced Memories for Edge-AI Embedded Systems	0	0.34	2019
A Design Framework for Thermal-Aware Power Delivery Network in 3D MPSoCs with Integrated Flow Cell Arrays	0	0.34	2019
An Associativity-Agnostic in-Cache Computing Architecture Optimized for Multiplication	1	0.40	2019
Rramspec: A Design Space Exploration Framework For High Density Resistive Ram	0	0.34	2019
Switching Event Detection and Self-Termination Programming Circuit for Energy Efficient ReRAM Memory Arrays	2	0.47	2019
Design Methodology For Area And Energy Efficient Oxram-Based Non-Volatile Flip-Flop	1	0.39	2017
High density emerging resistive memories: What are the limits?	1	0.38	2017
Architecture, design and technology guidelines for crosspoint memories	3	0.50	2017
Capacitor based SneakPath compensation circuit for transistor-less ReRAM architectures	2	0.42	2016
SneakPath compensation circuit for programming and read operations in RRAM-based CrossPoint architectures	3	0.53	2015