Paper Info
Title
Analysis of Functional Errors Produced by Long-Term Workload-Dependent BTI Degradation in Ultralow Power Processors
Abstract
Aging effects in digital circuits change the switching characteristics of their transistors, resulting in timing violations that can lead to functional errors at the system level. In particular, bias temperature instability (BTI) is a degradation effect that changes the threshold voltage of transistors. Its effect is more prevalent as the scaling of transistor dimensions progresses. In this work, we present a method to enable defect-centric long-term modeling of BTI degradation that takes into account the effects of concrete workloads at the processor data path level. Based on this study, we propose a novel design flow to link the impact of BTI degradation at the transistor ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\Delta {}V_{\text {th}}}$ </tex-math></inline-formula> ), processor data path (e.g., maximum frequency) and application-functionality levels. This flow may be used to improve system correctness over the entire device lifetime, avoiding unsafe working points, or to achieve a graceful degradation of system characteristics. Our design flow is applicable to all types of digital circuits, including high-performance processors. However, in this specific work we focus on the domain of biosignal processing applications for wireless body sensor networks (WBSNs), the pseudoperiodic nature of which interacts with the partially recoverable nature of BTI. Our results in this domain show, for a 32-nm implementation, a variation of up to 54.6 mV in the threshold voltage of the circuit transistors after one year of continuous operation, with an impact of 8.4% in the maximum safe operating frequency. Such effects are expected to strongly worsen for longer lifetimes and more scaled technology nodes.
Year
DOI
Venue
2020
10.1109/TVLSI.2020.3003471
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Keywords
DocType
Volume
Transistors,Degradation,Computational modeling,Integrated circuit modeling,Stress,Program processors,Timing
Journal
28
Issue
ISSN
Citations 
10
1063-8210
0
PageRank 
References 
Authors
0.34
0
7
Name
Order
Citations
PageRank
Loris Duch132.10
Miguel Peón Quirós2323.83
Pieter Weckx35216.96
A. Levisse4258.74
Rubén Braojos500.34
Francky Catthoor63932423.30
D. Atienza718224.26