Author Info
Name
Affiliation
Papers
RATHNA, G.N.
Dept. of Electr. Eng., Indian Inst. of Sci., Bangalore, India|c|
1
Collaborators
Citations 
PageRank 
2
0
0.34
Referers 
Referees 
References 
0
6
3
Title
Citations
PageRank
Year
A methodology for architecture synthesis of cascaded IIR filters on TLU FPGAs00.341994