Author Info
Name
Affiliation
Papers
HAFIJUR RAHMAN
Dept. of Electr. Eng., Arizona State Univ., Tempe, AZ, USA|c|
1
Collaborators
Citations 
PageRank 
1
11
0.86
Referers 
Referees 
References 
31
14
4
Title
Citations
PageRank
Year
A leakage estimation and reduction technique for scaled CMOS logic circuits considering gate-leakage110.862004