Kumar Y. B. Nithin

Author Info

Name	Affiliation	Papers
KUMAR Y. B. NITHIN	Dept. of Electronics and Communication, National Institute of Technology, Goa, India	23
Collaborators	Citations	PageRank
43	14	8.21
Referers	Referees	References
32	140	63

Search Limit

100140

Publications (23 rows)

Collaborators (43 rows)

Referers (32 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
+/- 0.5 V, 254 Mu W Second-Order Tunable Biquad Low-Pass Filter With 7.3 Fj Fom Using A Novel Low-Voltage Fully Balanced Current-Mode Circuit	0	0.34	2021
Quantization aware approximate multiplier and hardware accelerator for edge computing of deep learning applications	0	0.34	2021
A Novel Complex Filter Design With Dual Feedback For High Frequency Wireless Receiver Applications	1	0.36	2021
A 1-V, 3-GHz Strong-Arm Latch Voltage Comparator for High Speed Applications	0	0.34	2020
Design of Approximate Booth Squarer for Error-Tolerant Computing	0	0.34	2020
Reversible Logic Implementation of Image Denoising for Grayscale Images	0	0.34	2020
A Wideband 12 Phase Ring Oscillator for 5G Applications.	0	0.34	2020
Power Saving Scheme for Process Corner Calibrated Standard Cell Based Flash ADC in Wireless Surveillance Applications.	0	0.34	2020
An Asynchronous Analog to Digital Converter for Video Camera Applications	0	0.34	2019
Design and Implementation of Reversible Logic based RGB to Gray scale Color Space Converter	0	0.34	2018
An Asynchronous Analog to Digital Converter for Surveillance Camera Applications	0	0.34	2018
A Novel Low Power G m-C Continuous-Time Analog Filter with Wide Tuning Range.	0	0.34	2018
Design and Analysis of Approximate Multipliers for Error-Tolerant Applications	0	0.34	2018
Characterization of a Novel Low Leakage Power-Efficient Asymmetric 7T SRAM Cell	0	0.34	2018
Low Power Approximate Multipliers With Truncated Carry Propagation for LSBs	0	0.34	2018
Design of 5-Bit Flash ADC Using Multiple Input Standard Cell Gates for Large Input Swing.	0	0.34	2017
A 0.5 V Low Power OTA-C Low Pass Filter for ECG Detection.	0	0.34	2017
Design of Low Power 4-Bit 400MS/s Standard Cell Based Flash ADC.	1	0.45	2017
Design and Analysis of Novel InSb/Si Heterojunction Double Gate Tunnel Field Effect Transistor	0	0.34	2016
Characterization of a Novel Low Leakage Power and Area Efficient 7T SRAM Cell	0	0.34	2016
Design of Low Power 5-Bit Hybrid Flash ADC	2	0.42	2016
A Gracefully Degrading and Energy-Efficient Fault Tolerant NoC Using Spare Core	10	0.56	2016
FPGA realisation of PSNR and BPP driven Adaptive Compression and Encryption Algorithm for RGB Images.	0	0.34	2016