Name
Abstract | ||
|---|---|---|
This paper proposes an asynchronous analog to digital converter (ADC) for surveillance camera applications. The proposed architecture is based on non-uniform sampling, whose sampling instants depend on the amplitude of the input voltage. The proposed design has the power performance advantage for an input voltage close to the upper reference voltage. Thus, the proposed architecture is suitable for the applications in which the input signal rarely assumes voltage values closer to the lower reference voltage. The design is simulated, at the transistor level, in a 180-nm CMOS technology. The results show that about 96.7% of the power can be saved in the best case (input voltage in the vicinity of upper reference voltage) when compared to a conventional flash ADC. |
Year | DOI | Venue |
|---|---|---|
2018 | 10.1109/ISVLSI.2018.00039 | 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) |
Keywords | Field | DocType |
Analog to Digital Converter (ADC),Asynchronous Logic,Double-tail Comparator | Asynchronous communication,Computer science,Voltage reference,Voltage,Analog-to-digital converter,Electronic engineering,CMOS,Flash ADC,Transistor,Very-large-scale integration | Conference |
ISSN | ISBN | Citations |
2159-3469 | 978-1-5386-7100-9 | 0 |
PageRank | References | Authors |
0.34 | 7 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| R. K. Siddharth | 1 | 2 | 3.13 |
| Sunil R. | 2 | 0 | 0.34 |
| Kumar Y. B. Nithin | 3 | 14 | 8.21 |
| M. H. Vasantha | 4 | 12 | 7.06 |
| Edoardo Bonizzoni | 5 | 162 | 47.30 |