| A 0.5 V Low-Power All-Digital Phase-Locked Loop In 65 Nm Complementary Metal-Oxide-Semiconductor Process | 0 | 0.34 | 2019 |
| A Study on Coarse Stage Bit Allocation to Improve Power Efficiency of a 10-bit Coarse-Fine SAR ADC Implemented in 65nm CMOS Process for Environmental Sensing Applications | 0 | 0.34 | 2018 |
| A gm/ID Based Algorithm for the Design of CMOS Miller Operational Amplifiers in 65 nm Technology. | 0 | 0.34 | 2018 |
| An Ultra-Low Power Direct Active-RF Detection Wake-Up Receiver with Noise-Cancelling Envelope Detector in 65 nm CMOS Process | 0 | 0.34 | 2018 |
| A 2.4 GHz Energy-efficient Short-range Receiver with Wake-up and Multiple Gain Settings for Wireless Sensor Networks | 0 | 0.34 | 2018 |
| Design and Implementation of a Thermoelectric Energy Harvesting Interface Circuit with Maximum Power Point Tracking and Self-Startup Capability for Wireless Sensor Nodes | 0 | 0.34 | 2018 |
| Low Power Converter for Capacitive Sensors Using Capacitance-to-Pulse Width Modulation | 0 | 0.34 | 2018 |
| A 0.5V Low-Power All-Digital Phase-Locked Loop in 65nm CMOS Process for Wireless Sensing Applications | 0 | 0.34 | 2018 |
| Power Optimization of a 0.5V 0.286-to-18MHz ADPLL in 65nm CMOS Process | 0 | 0.34 | 2018 |
| Smart-wire: A 0.5V 44uW 0°C to 100°C power-line energy harvesting sensor node | 0 | 0.34 | 2017 |
| Improving an undergraduate laboratory course for semiconductor device theory to enhance an IC design program. | 0 | 0.34 | 2013 |
