A 0.5 V Low-Power All-Digital Phase-Locked Loop In 65 Nm Complementary Metal-Oxide-Semiconductor Process - Citegraph

Paper Info

Title
A 0.5 V Low-Power All-Digital Phase-Locked Loop In 65 Nm Complementary Metal-Oxide-Semiconductor Process

Abstract
A clock generator is an important part of most systems as it is used for synchronization and data processing. For low-power operations, an all-digital phase-locked loop (ADPLL) is a suitable implementation of a clock generator for wireless sensing applications. Design decisions in different levels of abstraction were done to further reduce the power of an implemented ADPLL. It was shown that its power consumption can be minimized by at most 70%. Moreover, the output frequency of the ADPLL ranges from 0.286-18 MHz with a power consumption of 4.606 mu W at 18 MHz.

Year	DOI	Venue
2019	10.1166/jolpe.2019.1596	JOURNAL OF LOW POWER ELECTRONICS
Keywords	Field	DocType
ADPLL, DCO, Power Optimization	Phase-locked loop,CMOS,Electronic engineering,Engineering,Optoelectronics	Journal
Volume	Issue	ISSN
15	1	1546-1998
Citations	PageRank	References
0	0.34	0
Authors
10

Authors (10 rows)

Cited by (0 rows)

References (0 rows)

Name	Order	Citations	PageRank
Fredrick Angelo R. Galapon	1	0	0.34
Mark Allen D. C. Agaton	2	0	0.34
Arcel G. Leynes	3	0	0.34
Lemuel Neil M. Noveno	4	0	0.34
Anastacia B. Alvarez	5	39	8.83
Chris Vincent J. Densing	6	0	0.68
John Richard E. Hizon	7	2	3.84
m d rosales	8	2	1.79
Maria Theresa G. de Leon	9	2	4.50
Rico Jossel M. Maestro	10	0	3.72

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