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TACO, R.
Author Info
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Name
Affiliation
Papers
TACO, R.
Univ Calabria, Dept Informat Modeling Elect & Syst Engn, I-87036 Arcavacata Di Rende, Italy
6
Collaborators
Citations
PageRank
8
9
2.37
Referers
Referees
References
12
40
26
Publications (6 rows)
Collaborators (8 rows)
Referers (12 rows)
Referees (40 rows)
Title
Citations
PageRank
Year
Silicon Evaluation of Multimode Dual Mode Logic for PVT-Aware Datapaths
0
0.34
2020
An 88-fJ/40-MHz [0.4 V]–0.61-pJ/1-GHz [0.9 V] Dual-Mode Logic 8 <inline-formula> <tex-math notation="LaTeX">$\times$ </tex-math></inline-formula> 8 bit Multiplier Accumulator With a Self-Adjustment Mechanism in 28-nm FD-SOI
0
0.34
2019
Extended exploration of low granularity back biasing control in 28nm UTBB FD-SOI technology
3
0.44
2016
Gate-level body biasing for subthreshold logic circuits: analytical modeling and design guidelines
0
0.34
2015
Ultra-low-voltage self-body biasing scheme and its application to basic arithmetic circuits
1
0.40
2015
Dynamic gate-level body biasing for subthreshold digital design
5
0.51
2014
1