Balsara, P.T. - Citegraph

Author Info

Name	Affiliation	Papers
BALSARA, P.T.	UNIV TEXAS,DEPT ELECTR ENGN,RICHARDSON,TX 75083	21
Collaborators	Citations	PageRank
32	297	58.67
Referers	Referees	References
757	275	120

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100757

Publications (21 rows)

Collaborators (32 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Minimum Phase Wide Output Range Digitally Controlled SIDO Boost Converter	0	0.34	2015
IIP2 requirements in 4G LTE handset receivers	1	0.40	2013
94.6% peak efficiency DCM buck converter with fast adaptive dead-time control	3	0.59	2013
Novel analysis of passive mixer output impedance using switched-capacitor techniques	0	0.34	2013
Linear Time-Variant Modeling and Analysis of All-Digital Phase-Locked Loops	5	0.48	2012
Hybrid NEMS-CMOS DC-DC Converter for Improved Area and Power Efficiency	1	0.36	2012
Multi-clock domain analysis and modeling of all-digital frequency synthesizers	4	0.46	2011
Recombination of Envelope and Phase Paths in Wideband Polar Transmitters	13	0.80	2010
Time-Domain Modeling of an RF All-Digital PLL	21	1.34	2008
A Low Power and Low Quantization Noise Digital Sigma-Delta Modulator for Wireless Transmitters	1	0.59	2007
All-Digital PLL With Ultra Fast Settling	51	3.70	2007
A Low Area and Low Power Digital Band-Pass Sigma-Delta Modulator for Wireless Transmitters	2	0.39	2007
VLSI Architecture for Matrix Inversion using Modified Gram-Schmidt based QR Decomposition	50	3.58	2007
IIP2 and DC Offsets in the Presence of Leakage at LO Frequency	16	2.08	2006
A Reconfigurable CAM Architecture for Network Search Engines	3	0.46	2006
Just-in-time gain estimation of an RF digitally-controlled oscillator	2	1.31	2003
Just-in-time gain estimation of an RF digitally-controlled oscillator for digital direct frequency modulation	30	13.53	2003
Digitally controlled oscillator (DCO)-based architecture for RF frequency synthesis in a deep-submicrometer CMOS Process	71	24.83	2003
High performance low power array multiplier using temporal tiling	20	2.02	1999
An architecture for a DSP field-programmable gate array	3	0.76	1995
Systolic & semi-systolic digit serial multipliers	0	0.34	1987