| Reducing DRAM Refresh Power Consumption by Runtime Profiling of Retention Time and Dual-row Activation | 2 | 0.35 | 2020 |
| A Novel In-DRAM Accelerator Architecture for Binary Neural Network | 0 | 0.34 | 2020 |
| 25.3 A 1.35V 5.0Gb/s/pin GDDR5M with 5.4mW standby power and an error-adaptive duty-cycle corrector | 3 | 0.45 | 2014 |
