Name
Title | ||
|---|---|---|
25.3 A 1.35V 5.0Gb/s/pin GDDR5M with 5.4mW standby power and an error-adaptive duty-cycle corrector |
Abstract | ||
|---|---|---|
The demand for high-bandwidth memories is increasing with an increase in the need for high-performance systems. Wide-I/O memory and GDDR5 are two types of high-bandwidth memories. GDDR5 is more compatible than wide I/O for contemporary systems, such as graphics cards and game consoles. The datarate of GDDR5 has reached 7Gb/s/pin. However, the power consumption and cost have increased owing to high-performance-oriented designs, die penalties, and additional test costs. DDR4 is an alternative low-cost memory with high performance in the range of 2.4 to 3.2Gb/s/pin [1]. However it is difficult for DDR4 DRAM to raise the 3.2Gb/s/pin bin portion to lower the cost. In DRAMs, the standby power and self-refresh power are more important than the operating power because DRAMs are mainly in the standby or self-refresh mode in systems. As the operating speed increases, the data window is narrowed, and the jitter increases. Therefore, a duty-cycle corrector (DCC) is employed to increase the data window when the external clock duty cycle is distorted in GDDR5 [2]. The bang-bang jitter caused by the DCC is inevitable even if the external clock duty ratio is exactly 50%. Sometimes the DCC may distort the data window because of an internal DCC offset. This paper presents a GDDR5M (mainstream) memory for graphics cards and a small-outline dual-inline memory module (SO-DIMM). The standby power is managed by the auto-sync mode. Additionally, the architecture of GDDR5M is similar to that of DDR4, and not GDDR5. The error-adaptive DCC can remove the initial duty-cycle offset automatically and remove the bang-bang jitter when the duty cycle of the external clock is not distorted. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/ISSCC.2014.6757502 | Solid-State Circuits Conference Digest of Technical Papers |
Keywords | DocType | ISSN |
dram chips,clock distribution networks,jitter,ddr4 dram,gddr5m mainstream memory,so-dimm,autosync mode,bang-bang jitter,bit rate 5.0 gbit/s,contemporary systems,data window,datarate,duty-cycle offset,error-adaptive dcc,error-adaptive duty-cycle corrector,external clock duty ratio,game consoles,graphics cards,high-bandwidth memories,high-performance systems,power 5.4 mw,power consumption,self-refresh power,small-outline dual-inline memory module,standby power,voltage 1.35 v,wide-i-o memory | Conference | 0193-6530 |
Citations | PageRank | References |
3 | 0.45 | 3 |
Authors | ||
19 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Hyun-Woo Lee | 1 | 162 | 43.02 |
| Junyoung Song | 2 | 40 | 11.42 |
| sangah hyun | 3 | 3 | 0.45 |
| seunggeun baek | 4 | 3 | 0.45 |
| yuri lim | 5 | 3 | 0.45 |
| jungwan lee | 6 | 3 | 0.45 |
| minsu park | 7 | 3 | 0.79 |
| haerang choi | 8 | 5 | 1.14 |
| changkyu choi | 9 | 3 | 0.45 |
| jinyoup cha | 10 | 3 | 0.45 |
| Jaeil Kim | 11 | 63 | 5.46 |
| Seung-Wook Kwack | 12 | 18 | 2.78 |
| yonggu kang | 13 | 3 | 0.45 |
| junghoon park | 14 | 3 | 0.79 |
| Jin-Hee Cho | 15 | 26 | 4.15 |
| Chulwoo Kim | 16 | 9 | 4.86 |
| Yunsaing Kim | 17 | 39 | 5.45 |
| Byongtae Chung | 18 | 76 | 7.44 |
| s hong | 19 | 54 | 4.05 |