M. H. Vasantha - Citegraph

Author Info

Name	Affiliation	Papers
M. H. VASANTHA	Dept. of Electronics and Communication, National Institute of Technology, Goa, India	20
Collaborators	Citations	PageRank
45	12	7.06
Referers	Referees	References
23	159	66

Search Limit

100159

Publications (20 rows)

Collaborators (45 rows)

Referers (23 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
A 1-V, 10-bit, 250 MS/s, Current-Steering Segmented DAC for Video Applications	0	0.34	2021
+/- 0.5 V, 254 Mu W Second-Order Tunable Biquad Low-Pass Filter With 7.3 Fj Fom Using A Novel Low-Voltage Fully Balanced Current-Mode Circuit	0	0.34	2021
A 1-V, 5-Bit, 180-Mu W, Differential Pulse Position Modulation Adc In 65-Nm Cmos Process	0	0.34	2021
A 1 V Double-Balanced Mixer for 2.4-2.5 GHz ISM Band Applications	0	0.34	2021
Quantization aware approximate multiplier and hardware accelerator for edge computing of deep learning applications	0	0.34	2021
Design of Approximate Booth Squarer for Error-Tolerant Computing	0	0.34	2020
A Novel Single Event Upset Tolerant 12T Memory Cell for Aerospace Applications	0	0.34	2020
Two-Step Flash ADC Using Standard Cell Based Flash ADCs	0	0.34	2019
An Asynchronous Analog to Digital Converter for Video Camera Applications	0	0.34	2019
Performance Enhancement of Split Length Compensated Operational Amplifiers.	0	0.34	2018
Design and Implementation of Reversible Logic based RGB to Gray scale Color Space Converter	0	0.34	2018
FPGA Implementation of Square and Cube Architecture Using Vedic Mathematics	0	0.34	2018
An Asynchronous Analog to Digital Converter for Surveillance Camera Applications	0	0.34	2018
Design of Area-Power-Delay Efficient Square Root Carry Select Adder	0	0.34	2018
Design and Analysis of Approximate Multipliers for Error-Tolerant Applications	0	0.34	2018
Characterization of a Novel Low Leakage Power-Efficient Asymmetric 7T SRAM Cell	0	0.34	2018
Design and Analysis of Novel InSb/Si Heterojunction Double Gate Tunnel Field Effect Transistor	0	0.34	2016
Characterization of a Novel Low Leakage Power and Area Efficient 7T SRAM Cell	0	0.34	2016
Design of Low Power 5-Bit Hybrid Flash ADC	2	0.42	2016
A Gracefully Degrading and Energy-Efficient Fault Tolerant NoC Using Spare Core	10	0.56	2016