Author Info
Name
Affiliation
Papers
DONGYANG JIANG
State-Key Laboratory of Analog and Mixed-Signal VLSI, Institute of Microelectronics, University of Macau, Macau, China
3
Collaborators
Citations 
PageRank 
10
5
1.22
Referers 
Referees 
References 
19
0
0
Title
Citations
PageRank
Year
A Time-Interleaved 2<sup>nd</sup>-Order ΔΣ Modulator Achieving 5-MHz Bandwidth and 86.1-dB SNDR Using Digital Feed-Forward Extrapolation00.342021
A 5MHz-BW, 86.1dB-SNDR 4X Time-Interleaved 2<sup>nd</sup>-Order ΔΣ Modulator with Digital Feedforward Extrapolation in 28nm CMOS00.342020
A 76.6-dB-SNDR 50-MHz-BW 29.2-mW Multi-Bit CT Sturdy MASH With DAC Non-Linearity Tolerance50.552020