Name
Title | ||
|---|---|---|
A Time-Interleaved 2<sup>nd</sup>-Order ΔΣ Modulator Achieving 5-MHz Bandwidth and 86.1-dB SNDR Using Digital Feed-Forward Extrapolation |
Abstract | ||
|---|---|---|
This article presents a
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time-interleaved (TI) 2nd-order discrete-time (DT) delta-sigma modulator (DSM). We propose a digital feed-forward extrapolation by first digitizing the internal analog nodes’ information from one channel, and then extrapolating the other channels in the digital domain. As a result, this DSM only needs two operational amplifiers (op-amps) to realize four interleaving paths, thus reducing analog hardware overheads. Meanwhile, we linearize the digital feed-forward paths through injected dithering. We present the derivation of extrapolating TI DSM starting from a single-channel DSM, while we also list and compare several conventional TI approaches. Implemented in 28-nm CMOS, this modulator achieves an equivalent output-sampling rate of 2.08 GS/s,
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oversampling ratio (OSR), and a signal to noise and distortion ratio (SNDR)/spurious-free dynamic range (SFDR) of 86.1 dB/98 dB with 5-MHz bandwidth (BW). The power consumption is 23.1 mW, which results in a Schreier Figure of Merit (FoM) of 169.5 dB. |
Year | DOI | Venue |
|---|---|---|
2021 | 10.1109/JSSC.2021.3060859 | IEEE Journal of Solid-State Circuits |
Keywords | DocType | Volume |
Analog-to-digital converter (ADC),data weighting average (DWA),delta-sigma modulator (DSM),digital bank filters,digital-to-analog converter (DAC),discrete-time (DT),dithering,dynamic element matching (DEM),extrapolation,noise-coupling,time-domain analysis,time-interleaved (TI) | Journal | 56 |
Issue | ISSN | Citations |
8 | 0018-9200 | 0 |
PageRank | References | Authors |
0.34 | 0 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Dongyang Jiang | 1 | 5 | 1.22 |
| Liang Qi | 2 | 4 | 5.15 |
| Sai-Weng Sin | 3 | 0 | 0.34 |
| Franco Maloberti | 4 | 0 | 0.34 |
| Rui Paulo Martins | 5 | 43 | 7.21 |