A 1.7 GHz Fractional-N Frequency Synthesizer Based on a Multiplying Delay-Locked Loop | 15 | 0.81 | 2015 |
Analysis and Design of Low-Jitter Digital Bang-Bang Phase-Locked Loops | 16 | 0.95 | 2014 |
21.1 A 1.7GHz MDLL-based fractional-N frequency synthesizer with 1.4ps RMS integrated jitter and 3mW power using a 1b TDC | 10 | 1.08 | 2014 |
Exploiting Stochastic Resonance to Enhance the Performance of Digital Bang-Bang PLLs | 8 | 0.70 | 2013 |
An efficient method to compute phase-noise in injection-locked frequency dividers | 0 | 0.34 | 2013 |
Minimum-jitter design of bang-bang PLLs in the presence of 1/f2 and 1/f3 DCO noise | 0 | 0.34 | 2013 |