Title
Minimum-jitter design of bang-bang PLLs in the presence of 1/f2 and 1/f3 DCO noise
Abstract
Digital phase-locked loops based on bang-bang phase detectors are attractive candidates for frequency synthesizers and clock multipliers because of their simplicity and low power consumption. However, being nonlinear systems, they are proved difficult to analyze and prone to the generation of limit cycles. Under the presence of phase noise originating from the controlled oscillator with 1/f2 and 1/f3 spectral shapes, simple expressions of the output jitter as a function of the loop parameters are developed which allow us to avoid limit cycles and to optimize the design to minimize output jitter.
Year
DOI
Venue
2013
10.1109/ISCAS.2013.6571810
international symposium on circuits and systems
Keywords
Field
DocType
1/f noise,digital phase locked loops,jitter,limit cycles,nonlinear systems,phase locked oscillators,phase noise,1/f2 DCO noise,1/f3 DCO noise,bang-bang phase detectors,clock multipliers,digital phase-locked loops,digitally-controlled oscillator,frequency synthesizers,nonlinear systems,output jitter,phase noise
Oscillation,Bang bang,Nonlinear system,Expression (mathematics),Oscillator phase noise,Control theory,Computer science,Phase noise,Electronic engineering,Jitter,Detector
Conference
ISSN
ISBN
Citations 
0271-4302
978-1-4673-5760-9
0
PageRank 
References 
Authors
0.34
7
4
Name
Order
Citations
PageRank
giovanni marucci1494.23
Salvatore Levantino235143.23
Paolo Maffezzoni322627.07
Carlo Samori434939.76