Author Info
Name
Affiliation
Papers
JINYONG CHOI
Samsung Electronics, Hwaseong, Korea
2
Collaborators
Citations 
PageRank 
60
0
0.68
Referers 
Referees 
References 
0
29
2
Title
Citations
PageRank
Year
A 16gb Sub-1v 7.14gb/S/Pin Lpddr5 Sdram Applying A Mosaic Architecture With A Short-Feedback 1-Tap Dfe, An Fss Bus With Low-Level Swing And An Adaptively Controlled Body Biasing In A 3rd-Generation 10nm Dram00.342021
5.5 A 2.1e<sup>−</sup> Temporal Noise and −105dB Parasitic Light Sensitivity Backside-Illuminated 2.3µm-Pixel Voltage-Domain Global Shutter CMOS Image Sensor Using High-Capacity DRAM Capacitor Technology00.342020